From: Leonid M. <l.m...@sa...> - 2013-11-19 10:08:15
|
It is done as a copy of Scorpion CPU due to I have no documentation. Thus corner cases like L2CC PMU might not work but basic set we need is suppored. The opreport output from Krait-based device looks realisic: CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 (No unit mask) count 100000 CPU_CYCLES:100000| samples| %| ------------------ 452276 42.5950 no-vmlinux 312804 29.4596 video-screen CPU_CYCLES:100000| samples| %| ------------------ 116443 37.2255 libpthread-2.13.so 90191 28.8331 libglib-2.0.so.0.3200.3 33572 10.7326 libecore.so.1.7.99 32668 10.4436 libc-2.13.so 14625 4.6755 libdbus-1.so.3.7.2 .... Signed-off-by: Leonid Moiseichuk <l.m...@sa...> --- events/Makefile.am | 1 + events/arm/armv7-krait/events | 94 +++++++++++++++++++++++++++++++++++++++ events/arm/armv7-krait/unit_masks | 5 +++ libop/op_cpu_type.c | 1 + libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/ophelp.c | 6 +++ 7 files changed, 109 insertions(+) create mode 100644 events/arm/armv7-krait/events create mode 100644 events/arm/armv7-krait/unit_masks diff --git a/events/Makefile.am b/events/Makefile.am index 3028c2f19ac9..ad45642049dd 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -53,6 +53,7 @@ event_files = \ arm/armv7/events arm/armv7/unit_masks \ arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ + arm/armv7-krait/events arm/armv7-krait/unit_masks \ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events new file mode 100644 index 000000000000..a5dd109f35ea --- /dev/null +++ b/events/arm/armv7-krait/events @@ -0,0 +1,94 @@ +# ARM V7 events +# From Krait Processor Family Programmer's Reference Manual (PRM) +# WARNING: that is ad-hoc change which should be sync with reference manual +include:arm/armv7-common + +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU + +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle + +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier + +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_DUAL_CYCLE : Krait VIU dual cycle +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_SINGLE_CYCLE : Krait VIU single cycle +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAR_STALL_CYCLES : Krait VX pipe WAR cycles +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAW_STALL_CYCLES : Krait VX pipe WAW cycles +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_RAW_STALL_CYCLES : Krait VX pipe RAW cycles +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_LOAD_USE_STALL : Krait VX pipe load use stall +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAR_STALL_CYCLES : Krait VS pipe WAR stall cycles +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAW_STALL_CYCLES : Krait VS pipe WAW stall cycles +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_RAW_STALL_CYCLES : Krait VS pipe RAW stall cycles +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_INV_OPERATION : Krait invalid operation exceptions +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DIV_BY_ZERO : Krait divide by zero exceptions +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VX_PIPE : Krait conditional instruction fail VX pipe +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VS_PIPE : Krait conditional instruction fail VS pipe +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_OVERFLOW : Krait overflow exceptions +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_UNDERFLOW : Krait underflow exceptions +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DENORM : Krait denorm exceptions + +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks new file mode 100644 index 000000000000..422e240d46f1 --- /dev/null +++ b/events/arm/armv7-krait/unit_masks @@ -0,0 +1,5 @@ +# ARM V7 PMNC possible unit masks +# WARNING: that is ad-hoc change which should be sync with reference manual +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 4bb34b72fb6b..9627882f1b7f 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -110,6 +110,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 }, { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 }, { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 }, diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 4703fa92cd88..f92eb7b08bc0 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -90,6 +90,7 @@ typedef enum { CPU_WESTMERE, /* Intel Westmere microarchitecture */ CPU_ARM_SCORPION, /**< ARM SCORPION */ CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ + CPU_ARM_KRAIT, /**< ARM KRAIT */ CPU_SANDYBRIDGE, /* Intel Sandy-Bridge microarchitecture */ CPU_TILE_TILE64, /**< Tilera TILE64 family */ CPU_TILE_TILEPRO, /**< Tilera TILEPro family (Pro64 or Pro36) */ diff --git a/libop/op_events.c b/libop/op_events.c index 39c710df2b41..358a154d127c 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_AVR32: case CPU_ARM_SCORPION: case CPU_ARM_SCORPIONMP: + case CPU_ARM_KRAIT: descr->name = "CPU_CYCLES"; break; diff --git a/utils/ophelp.c b/utils/ophelp.c index 7543c6f37b7b..01b5ca4f9409 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; break; + case CPU_ARM_KRAIT: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; + break; + case CPU_ARM_V7_CA9: event_doc = "See Cortex-A9 Technical Reference Manual\n" -- 1.8.3.2 |
From: Leonid M. <l.m...@sa...> - 2013-12-04 10:19:07
|
It is done as a copy of Scorpion CPU due to I have no documentation. Thus corner cases like L2CC PMU might not work but basic set we need is suppored. The opreport output from Krait-based device looks realisic: CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 (No unit mask) count 100000 CPU_CYCLES:100000| samples| %| ------------------ 452276 42.5950 no-vmlinux 312804 29.4596 video-screen CPU_CYCLES:100000| samples| %| ------------------ 116443 37.2255 libpthread-2.13.so 90191 28.8331 libglib-2.0.so.0.3200.3 33572 10.7326 libecore.so.1.7.99 32668 10.4436 libc-2.13.so 14625 4.6755 libdbus-1.so.3.7.2 .... Tested on device and using "make distcheck". Signed-off-by: Leonid Moiseichuk <l.m...@sa...> --- events/Makefile.am | 1 + events/arm/armv7-krait/events | 3 +++ events/arm/armv7-krait/unit_masks | 4 ++++ libop/op_cpu_type.c | 1 + libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/opcontrol | 0 utils/ophelp.c | 6 ++++++ 8 files changed, 17 insertions(+) create mode 100644 events/arm/armv7-krait/events create mode 100644 events/arm/armv7-krait/unit_masks mode change 100644 => 100755 utils/opcontrol diff --git a/events/Makefile.am b/events/Makefile.am index 3028c2f19ac9..ad45642049dd 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -53,6 +53,7 @@ event_files = \ arm/armv7/events arm/armv7/unit_masks \ arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ + arm/armv7-krait/events arm/armv7-krait/unit_masks \ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events new file mode 100644 index 000000000000..ec838c75c79b --- /dev/null +++ b/events/arm/armv7-krait/events @@ -0,0 +1,3 @@ +# ARM V7 events +# WARNING: just re-uses common ARM PMU codes as Stephen Boyd advised +include:arm/armv7-common diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks new file mode 100644 index 000000000000..4027469b029e --- /dev/null +++ b/events/arm/armv7-krait/unit_masks @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 4bb34b72fb6b..c37aeab6f965 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -128,6 +128,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 }, { "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 }, + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 4703fa92cd88..67e16dec403b 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -108,6 +108,7 @@ typedef enum { CPU_PPC_E500MC, /**< e500mc */ CPU_PPC_E6500, /**< e6500 */ CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */ + CPU_ARM_KRAIT, /**< ARM KRAIT */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index 39c710df2b41..358a154d127c 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_AVR32: case CPU_ARM_SCORPION: case CPU_ARM_SCORPIONMP: + case CPU_ARM_KRAIT: descr->name = "CPU_CYCLES"; break; diff --git a/utils/opcontrol b/utils/opcontrol old mode 100644 new mode 100755 diff --git a/utils/ophelp.c b/utils/ophelp.c index 7543c6f37b7b..01b5ca4f9409 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; break; + case CPU_ARM_KRAIT: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; + break; + case CPU_ARM_V7_CA9: event_doc = "See Cortex-A9 Technical Reference Manual\n" -- 1.8.3.2 |
From: Leonid M. <l.m...@sa...> - 2013-11-26 08:50:28
|
It is done as a copy of Scorpion CPU due to I have no documentation. Thus corner cases like L2CC PMU might not work but basic set we need is suppored. The opreport output from Krait-based device looks realisic: CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 (No unit mask) count 100000 CPU_CYCLES:100000| samples| %| ------------------ 452276 42.5950 no-vmlinux 312804 29.4596 video-screen CPU_CYCLES:100000| samples| %| ------------------ 116443 37.2255 libpthread-2.13.so 90191 28.8331 libglib-2.0.so.0.3200.3 33572 10.7326 libecore.so.1.7.99 32668 10.4436 libc-2.13.so 14625 4.6755 libdbus-1.so.3.7.2 .... make distcheck passed: oprofile-1.0.0git archives ready for distribution. Signed-off-by: Leonid Moiseichuk <l.m...@sa...> --- events/Makefile.am | 1 + events/arm/armv7-krait/events | 94 +++++++++++++++++++++++++++++++++++++++ events/arm/armv7-krait/unit_masks | 5 +++ libop/op_cpu_type.c | 1 + libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/opcontrol | 0 utils/ophelp.c | 6 +++ 8 files changed, 109 insertions(+) create mode 100644 events/arm/armv7-krait/events create mode 100644 events/arm/armv7-krait/unit_masks mode change 100644 => 100755 utils/opcontrol diff --git a/events/Makefile.am b/events/Makefile.am index 3028c2f19ac9..ad45642049dd 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -53,6 +53,7 @@ event_files = \ arm/armv7/events arm/armv7/unit_masks \ arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ + arm/armv7-krait/events arm/armv7-krait/unit_masks \ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events new file mode 100644 index 000000000000..a5dd109f35ea --- /dev/null +++ b/events/arm/armv7-krait/events @@ -0,0 +1,94 @@ +# ARM V7 events +# From Krait Processor Family Programmer's Reference Manual (PRM) +# WARNING: that is ad-hoc change which should be sync with reference manual +include:arm/armv7-common + +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU + +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle + +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier + +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_DUAL_CYCLE : Krait VIU dual cycle +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_SINGLE_CYCLE : Krait VIU single cycle +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAR_STALL_CYCLES : Krait VX pipe WAR cycles +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAW_STALL_CYCLES : Krait VX pipe WAW cycles +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_RAW_STALL_CYCLES : Krait VX pipe RAW cycles +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_LOAD_USE_STALL : Krait VX pipe load use stall +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAR_STALL_CYCLES : Krait VS pipe WAR stall cycles +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAW_STALL_CYCLES : Krait VS pipe WAW stall cycles +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_RAW_STALL_CYCLES : Krait VS pipe RAW stall cycles +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_INV_OPERATION : Krait invalid operation exceptions +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DIV_BY_ZERO : Krait divide by zero exceptions +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VX_PIPE : Krait conditional instruction fail VX pipe +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VS_PIPE : Krait conditional instruction fail VS pipe +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_OVERFLOW : Krait overflow exceptions +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_UNDERFLOW : Krait underflow exceptions +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DENORM : Krait denorm exceptions + +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks new file mode 100644 index 000000000000..422e240d46f1 --- /dev/null +++ b/events/arm/armv7-krait/unit_masks @@ -0,0 +1,5 @@ +# ARM V7 PMNC possible unit masks +# WARNING: that is ad-hoc change which should be sync with reference manual +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 4bb34b72fb6b..c37aeab6f965 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -128,6 +128,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 }, { "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 }, + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 4703fa92cd88..67e16dec403b 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -108,6 +108,7 @@ typedef enum { CPU_PPC_E500MC, /**< e500mc */ CPU_PPC_E6500, /**< e6500 */ CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */ + CPU_ARM_KRAIT, /**< ARM KRAIT */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index 39c710df2b41..358a154d127c 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_AVR32: case CPU_ARM_SCORPION: case CPU_ARM_SCORPIONMP: + case CPU_ARM_KRAIT: descr->name = "CPU_CYCLES"; break; diff --git a/utils/opcontrol b/utils/opcontrol old mode 100644 new mode 100755 diff --git a/utils/ophelp.c b/utils/ophelp.c index 7543c6f37b7b..01b5ca4f9409 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; break; + case CPU_ARM_KRAIT: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; + break; + case CPU_ARM_V7_CA9: event_doc = "See Cortex-A9 Technical Reference Manual\n" -- 1.8.3.2 |
From: Leonid M. <l.m...@sa...> - 2013-12-19 07:50:18
|
Hi, Do we have more inputs for v3 patch for Qualcomm Krait support? "Make distcheck" passed and guys who is working with Krait confirmed that oprofile and operf works fine. Thanks a lot, Leonid > -----Original Message----- > From: Leonid Moiseichuk [mailto:l.m...@sa...] > Sent: 04 December 2013 12:19 > To: opr...@li... > Cc: Leonid Moiseichuk > Subject: [PATCHv3] minimal Qualcomm Krait support > > It is done as a copy of Scorpion CPU due to I have no documentation. > Thus corner cases like L2CC PMU might not work but basic set we need is > suppored. The opreport output from Krait-based device looks realisic: ... |
From: Will D. <wil...@ar...> - 2013-12-20 17:11:22
|
On Thu, Dec 19, 2013 at 07:50:00AM +0000, Leonid Moiseichuk wrote: > Hi, Hi Leonid, > Do we have more inputs for v3 patch for Qualcomm Krait support? > "Make distcheck" passed and guys who is working with Krait confirmed that > oprofile and operf works fine. The patch looks fine to me, but can you please rework the commit message, since it still refers to the Scorpion events despite your latest changes. With that: Acked-by: Will Deacon <wil...@ar...> Cheers, Will |
From: Maynard J. <may...@us...> - 2013-12-19 15:45:56
|
Will, >From my perspective, the patch looks fine, but I defer to you (as the oprofile sub-maintainer for ARM) for final approval. Thanks. -Maynard On 12/04/2013 04:18 AM, Leonid Moiseichuk wrote: > It is done as a copy of Scorpion CPU due to I have no documentation. > Thus corner cases like L2CC PMU might not work but basic set we need > is suppored. The opreport output from Krait-based device looks realisic: > > CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) > Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 > (No unit mask) count 100000 > CPU_CYCLES:100000| > samples| %| > ------------------ > 452276 42.5950 no-vmlinux > 312804 29.4596 video-screen > CPU_CYCLES:100000| > samples| %| > ------------------ > 116443 37.2255 libpthread-2.13.so > 90191 28.8331 libglib-2.0.so.0.3200.3 > 33572 10.7326 libecore.so.1.7.99 > 32668 10.4436 libc-2.13.so > 14625 4.6755 libdbus-1.so.3.7.2 > .... > > Tested on device and using "make distcheck". > Signed-off-by: Leonid Moiseichuk <l.m...@sa...> > --- > events/Makefile.am | 1 + > events/arm/armv7-krait/events | 3 +++ > events/arm/armv7-krait/unit_masks | 4 ++++ > libop/op_cpu_type.c | 1 + > libop/op_cpu_type.h | 1 + > libop/op_events.c | 1 + > utils/opcontrol | 0 > utils/ophelp.c | 6 ++++++ > 8 files changed, 17 insertions(+) > create mode 100644 events/arm/armv7-krait/events > create mode 100644 events/arm/armv7-krait/unit_masks > mode change 100644 => 100755 utils/opcontrol > > diff --git a/events/Makefile.am b/events/Makefile.am > index 3028c2f19ac9..ad45642049dd 100644 > --- a/events/Makefile.am > +++ b/events/Makefile.am > @@ -53,6 +53,7 @@ event_files = \ > arm/armv7/events arm/armv7/unit_masks \ > arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ > arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ > + arm/armv7-krait/events arm/armv7-krait/unit_masks \ > arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ > arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ > arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ > diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events > new file mode 100644 > index 000000000000..ec838c75c79b > --- /dev/null > +++ b/events/arm/armv7-krait/events > @@ -0,0 +1,3 @@ > +# ARM V7 events > +# WARNING: just re-uses common ARM PMU codes as Stephen Boyd advised > +include:arm/armv7-common > diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks > new file mode 100644 > index 000000000000..4027469b029e > --- /dev/null > +++ b/events/arm/armv7-krait/unit_masks > @@ -0,0 +1,4 @@ > +# ARM V7 PMNC possible unit masks > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > index 4bb34b72fb6b..c37aeab6f965 100644 > --- a/libop/op_cpu_type.c > +++ b/libop/op_cpu_type.c > @@ -128,6 +128,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, > { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 }, > { "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 }, > + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, > }; > > static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > index 4703fa92cd88..67e16dec403b 100644 > --- a/libop/op_cpu_type.h > +++ b/libop/op_cpu_type.h > @@ -108,6 +108,7 @@ typedef enum { > CPU_PPC_E500MC, /**< e500mc */ > CPU_PPC_E6500, /**< e6500 */ > CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */ > + CPU_ARM_KRAIT, /**< ARM KRAIT */ > MAX_CPU_TYPE > } op_cpu; > > diff --git a/libop/op_events.c b/libop/op_events.c > index 39c710df2b41..358a154d127c 100644 > --- a/libop/op_events.c > +++ b/libop/op_events.c > @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > case CPU_AVR32: > case CPU_ARM_SCORPION: > case CPU_ARM_SCORPIONMP: > + case CPU_ARM_KRAIT: > descr->name = "CPU_CYCLES"; > break; > > diff --git a/utils/opcontrol b/utils/opcontrol > old mode 100644 > new mode 100755 > diff --git a/utils/ophelp.c b/utils/ophelp.c > index 7543c6f37b7b..01b5ca4f9409 100644 > --- a/utils/ophelp.c > +++ b/utils/ophelp.c > @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) > "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > break; > > + case CPU_ARM_KRAIT: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > case CPU_ARM_V7_CA9: > event_doc = > "See Cortex-A9 Technical Reference Manual\n" > |
From: Will D. <wil...@ar...> - 2013-12-20 17:12:42
|
On Thu, Dec 19, 2013 at 03:45:46PM +0000, Maynard Johnson wrote: > Will, > From my perspective, the patch looks fine, but I defer to you (as the > oprofile sub-maintainer for ARM) for final approval. Sure, I just reviewed v3 (one minor comment). Sorry for the delay, but I've finished work for Christmas now so I'm away from my desk (and trying to avoid reading email, unsuccessfully :). Will |
From: Leonid M. <l.m...@sa...> - 2013-12-23 07:38:41
|
> -----Original Message----- > From: Will Deacon [mailto:wil...@ar...] ... > The patch looks fine to me, but can you please rework the commit > message, since it still refers to the Scorpion events despite your > latest changes. Thanks for pointing, done. Leonid |
From: Leonid M. <l.m...@sa...> - 2014-01-10 13:57:54
|
> -----Original Message----- > From: Will Deacon [mailto:wil...@ar...] > Sent: 20 December 2013 19:11 > To: Leonid Moiseichuk > Cc: opr...@li... > Subject: Re: [PATCHv3] minimal Qualcomm Krait support ... > The patch looks fine to me, but can you please rework the commit > message, since it still refers to the Scorpion events despite your > latest changes. > > With that: > > Acked-by: Will Deacon <wil...@ar...> > > Cheers, > > Will Hi, Findings in v3 were fixed 23-Dec as v4, should I do something else? Best Wishes, Leonid |
From: Will D. <wil...@ar...> - 2014-01-10 15:03:30
|
On Fri, Jan 10, 2014 at 01:57:39PM +0000, Leonid Moiseichuk wrote: > > -----Original Message----- > > From: Will Deacon [mailto:wil...@ar...] > > Sent: 20 December 2013 19:11 > > To: Leonid Moiseichuk > > Cc: opr...@li... > > Subject: Re: [PATCHv3] minimal Qualcomm Krait support > ... > > The patch looks fine to me, but can you please rework the commit > > message, since it still refers to the Scorpion events despite your > > latest changes. > > > > With that: > > > > Acked-by: Will Deacon <wil...@ar...> > > > > Cheers, > > > > Will > > Hi, > > Findings in v3 were fixed 23-Dec as v4, should I do something else? I guess it just coincided with Christmas holiday for a lot of people, but Maynard should be able to apply v4 now with my Ack. Will |
From: Maynard J. <may...@us...> - 2014-01-10 15:35:08
|
On 01/10/2014 09:03 AM, Will Deacon wrote: > On Fri, Jan 10, 2014 at 01:57:39PM +0000, Leonid Moiseichuk wrote: >>> -----Original Message----- >>> From: Will Deacon [mailto:wil...@ar...] >>> Sent: 20 December 2013 19:11 >>> To: Leonid Moiseichuk >>> Cc: opr...@li... >>> Subject: Re: [PATCHv3] minimal Qualcomm Krait support >> ... >>> The patch looks fine to me, but can you please rework the commit >>> message, since it still refers to the Scorpion events despite your >>> latest changes. >>> >>> With that: >>> >>> Acked-by: Will Deacon <wil...@ar...> >>> >>> Cheers, >>> >>> Will >> >> Hi, >> >> Findings in v3 were fixed 23-Dec as v4, should I do something else? > > I guess it just coincided with Christmas holiday for a lot of people, but > Maynard should be able to apply v4 now with my Ack. > > Will > Patch applied. Thanks for the patch, Leonid, and thanks for the review help, Will and Stephen. -Maynard |
From: Leonid M. <l.m...@sa...> - 2013-12-23 07:38:00
|
It is done to support just common ARM PMU codes due to I have no documentation. Thus corner cases like L2CC PMU should not work but basic set we need usually is suppored. The opreport output from Krait-based device looks realisic: CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 (No unit mask) count 100000 CPU_CYCLES:100000| samples| %| ------------------ 452276 42.5950 no-vmlinux 312804 29.4596 video-screen CPU_CYCLES:100000| samples| %| ------------------ 116443 37.2255 libpthread-2.13.so 90191 28.8331 libglib-2.0.so.0.3200.3 33572 10.7326 libecore.so.1.7.99 32668 10.4436 libc-2.13.so 14625 4.6755 libdbus-1.so.3.7.2 .... Other developers reports that operf also works nice. Tested on device and using "make distcheck". Signed-off-by: Leonid Moiseichuk <l.m...@sa...> --- events/Makefile.am | 1 + events/arm/armv7-krait/events | 3 +++ events/arm/armv7-krait/unit_masks | 4 ++++ libop/op_cpu_type.c | 1 + libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + utils/opcontrol | 0 utils/ophelp.c | 6 ++++++ 8 files changed, 17 insertions(+) create mode 100644 events/arm/armv7-krait/events create mode 100644 events/arm/armv7-krait/unit_masks mode change 100644 => 100755 utils/opcontrol diff --git a/events/Makefile.am b/events/Makefile.am index 3028c2f19ac9..ad45642049dd 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -53,6 +53,7 @@ event_files = \ arm/armv7/events arm/armv7/unit_masks \ arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ + arm/armv7-krait/events arm/armv7-krait/unit_masks \ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events new file mode 100644 index 000000000000..ec838c75c79b --- /dev/null +++ b/events/arm/armv7-krait/events @@ -0,0 +1,3 @@ +# ARM V7 events +# WARNING: just re-uses common ARM PMU codes as Stephen Boyd advised +include:arm/armv7-common diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks new file mode 100644 index 000000000000..4027469b029e --- /dev/null +++ b/events/arm/armv7-krait/unit_masks @@ -0,0 +1,4 @@ +# ARM V7 PMNC possible unit masks +# +name:zero type:mandatory default:0x00 + 0x00 No unit mask diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 4bb34b72fb6b..c37aeab6f965 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -128,6 +128,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 }, { "Intel Silvermont microarchitecture", "i386/silvermont", CPU_SILVERMONT, 2 }, + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, }; static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index 4703fa92cd88..67e16dec403b 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -108,6 +108,7 @@ typedef enum { CPU_PPC_E500MC, /**< e500mc */ CPU_PPC_E6500, /**< e6500 */ CPU_SILVERMONT, /** < Intel Silvermont microarchitecture */ + CPU_ARM_KRAIT, /**< ARM KRAIT */ MAX_CPU_TYPE } op_cpu; diff --git a/libop/op_events.c b/libop/op_events.c index 39c710df2b41..358a154d127c 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) case CPU_AVR32: case CPU_ARM_SCORPION: case CPU_ARM_SCORPIONMP: + case CPU_ARM_KRAIT: descr->name = "CPU_CYCLES"; break; diff --git a/utils/opcontrol b/utils/opcontrol old mode 100644 new mode 100755 diff --git a/utils/ophelp.c b/utils/ophelp.c index 7543c6f37b7b..01b5ca4f9409 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; break; + case CPU_ARM_KRAIT: + event_doc = + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; + break; + case CPU_ARM_V7_CA9: event_doc = "See Cortex-A9 Technical Reference Manual\n" -- 1.8.3.2 |
From: Maynard J. <may...@us...> - 2013-11-25 18:58:11
|
Hi, Leonid, Thanks for the patch. *Will* is the ARM sub-maintainer for oprofile, so I'll have him review it. But a quick look reveals one issue . . . the new CPU type (in op_cpu_type.h) and corresponding description (in op_cpu_type.c) *must* be placed at the end of their respective list. Also, please run 'make distcheck' and verify it passes. Thanks. -Maynard On 11/19/2013 03:37 AM, Leonid Moiseichuk wrote: > It is done as a copy of Scorpion CPU due to I have no documentation. > Thus corner cases like L2CC PMU might not work but basic set we need > is suppored. The opreport output from Krait-based device looks realisic: > > CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) > Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 > (No unit mask) count 100000 > CPU_CYCLES:100000| > samples| %| > ------------------ > 452276 42.5950 no-vmlinux > 312804 29.4596 video-screen > CPU_CYCLES:100000| > samples| %| > ------------------ > 116443 37.2255 libpthread-2.13.so > 90191 28.8331 libglib-2.0.so.0.3200.3 > 33572 10.7326 libecore.so.1.7.99 > 32668 10.4436 libc-2.13.so > 14625 4.6755 libdbus-1.so.3.7.2 > .... > > Signed-off-by: Leonid Moiseichuk <l.m...@sa...> > --- > events/Makefile.am | 1 + > events/arm/armv7-krait/events | 94 +++++++++++++++++++++++++++++++++++++++ > events/arm/armv7-krait/unit_masks | 5 +++ > libop/op_cpu_type.c | 1 + > libop/op_cpu_type.h | 1 + > libop/op_events.c | 1 + > utils/ophelp.c | 6 +++ > 7 files changed, 109 insertions(+) > create mode 100644 events/arm/armv7-krait/events > create mode 100644 events/arm/armv7-krait/unit_masks > > diff --git a/events/Makefile.am b/events/Makefile.am > index 3028c2f19ac9..ad45642049dd 100644 > --- a/events/Makefile.am > +++ b/events/Makefile.am > @@ -53,6 +53,7 @@ event_files = \ > arm/armv7/events arm/armv7/unit_masks \ > arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ > arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ > + arm/armv7-krait/events arm/armv7-krait/unit_masks \ > arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ > arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ > arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ > diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events > new file mode 100644 > index 000000000000..a5dd109f35ea > --- /dev/null > +++ b/events/arm/armv7-krait/events > @@ -0,0 +1,94 @@ > +# ARM V7 events > +# From Krait Processor Family Programmer's Reference Manual (PRM) > +# WARNING: that is ad-hoc change which should be sync with reference manual > +include:arm/armv7-common > + > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > + > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > + > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > + > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_DUAL_CYCLE : Krait VIU dual cycle > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_SINGLE_CYCLE : Krait VIU single cycle > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAR_STALL_CYCLES : Krait VX pipe WAR cycles > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAW_STALL_CYCLES : Krait VX pipe WAW cycles > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_RAW_STALL_CYCLES : Krait VX pipe RAW cycles > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_LOAD_USE_STALL : Krait VX pipe load use stall > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAR_STALL_CYCLES : Krait VS pipe WAR stall cycles > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAW_STALL_CYCLES : Krait VS pipe WAW stall cycles > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_RAW_STALL_CYCLES : Krait VS pipe RAW stall cycles > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_INV_OPERATION : Krait invalid operation exceptions > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DIV_BY_ZERO : Krait divide by zero exceptions > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VX_PIPE : Krait conditional instruction fail VX pipe > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VS_PIPE : Krait conditional instruction fail VS pipe > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_OVERFLOW : Krait overflow exceptions > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_UNDERFLOW : Krait underflow exceptions > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DENORM : Krait denorm exceptions > + > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses > +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits > +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses > +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits > +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses > +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits > +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses > +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits > +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses > +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits > +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses > +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus > +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus > +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes > +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus > +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) > +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus > +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) > diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks > new file mode 100644 > index 000000000000..422e240d46f1 > --- /dev/null > +++ b/events/arm/armv7-krait/unit_masks > @@ -0,0 +1,5 @@ > +# ARM V7 PMNC possible unit masks > +# WARNING: that is ad-hoc change which should be sync with reference manual > +# > +name:zero type:mandatory default:0x00 > + 0x00 No unit mask > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > index 4bb34b72fb6b..9627882f1b7f 100644 > --- a/libop/op_cpu_type.c > +++ b/libop/op_cpu_type.c > @@ -110,6 +110,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, > { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, > { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, > + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, > { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 }, > { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 }, > { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 }, > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > index 4703fa92cd88..f92eb7b08bc0 100644 > --- a/libop/op_cpu_type.h > +++ b/libop/op_cpu_type.h > @@ -90,6 +90,7 @@ typedef enum { > CPU_WESTMERE, /* Intel Westmere microarchitecture */ > CPU_ARM_SCORPION, /**< ARM SCORPION */ > CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ > + CPU_ARM_KRAIT, /**< ARM KRAIT */ > CPU_SANDYBRIDGE, /* Intel Sandy-Bridge microarchitecture */ > CPU_TILE_TILE64, /**< Tilera TILE64 family */ > CPU_TILE_TILEPRO, /**< Tilera TILEPro family (Pro64 or Pro36) */ > diff --git a/libop/op_events.c b/libop/op_events.c > index 39c710df2b41..358a154d127c 100644 > --- a/libop/op_events.c > +++ b/libop/op_events.c > @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > case CPU_AVR32: > case CPU_ARM_SCORPION: > case CPU_ARM_SCORPIONMP: > + case CPU_ARM_KRAIT: > descr->name = "CPU_CYCLES"; > break; > > diff --git a/utils/ophelp.c b/utils/ophelp.c > index 7543c6f37b7b..01b5ca4f9409 100644 > --- a/utils/ophelp.c > +++ b/utils/ophelp.c > @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) > "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > break; > > + case CPU_ARM_KRAIT: > + event_doc = > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; > + break; > + > case CPU_ARM_V7_CA9: > event_doc = > "See Cortex-A9 Technical Reference Manual\n" > |
From: Will D. <wil...@ar...> - 2013-11-27 18:29:37
|
On Mon, Nov 25, 2013 at 06:57:50PM +0000, Maynard Johnson wrote: > Hi, Leonid, > Thanks for the patch. *Will* is the ARM sub-maintainer for oprofile, so I'll have him review it. But a quick look reveals one issue . . . the new CPU type (in op_cpu_type.h) and corresponding description (in op_cpu_type.c) *must* be placed at the end of their respective list. Also, please run 'make distcheck' and verify it passes. I also don't have any documentation for Krait, but I would be surprised if simply copying the event encodings over from Snapdragon was the correct thing to do. Rather than run the risk of producing potentially confusing profiling numbers, I'd really rather we had somebody from Qualcomm rubber-stamp this patch before we take it any further. Adding Stephen Boyd, in case he can help us. Will > On 11/19/2013 03:37 AM, Leonid Moiseichuk wrote: > > It is done as a copy of Scorpion CPU due to I have no documentation. > > Thus corner cases like L2CC PMU might not work but basic set we need > > is suppored. The opreport output from Krait-based device looks realisic: > > > > CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) > > Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 > > (No unit mask) count 100000 > > CPU_CYCLES:100000| > > samples| %| > > ------------------ > > 452276 42.5950 no-vmlinux > > 312804 29.4596 video-screen > > CPU_CYCLES:100000| > > samples| %| > > ------------------ > > 116443 37.2255 libpthread-2.13.so > > 90191 28.8331 libglib-2.0.so.0.3200.3 > > 33572 10.7326 libecore.so.1.7.99 > > 32668 10.4436 libc-2.13.so > > 14625 4.6755 libdbus-1.so.3.7.2 > > .... > > > > Signed-off-by: Leonid Moiseichuk <l.m...@sa...> > > --- > > events/Makefile.am | 1 + > > events/arm/armv7-krait/events | 94 +++++++++++++++++++++++++++++++++++++++ > > events/arm/armv7-krait/unit_masks | 5 +++ > > libop/op_cpu_type.c | 1 + > > libop/op_cpu_type.h | 1 + > > libop/op_events.c | 1 + > > utils/ophelp.c | 6 +++ > > 7 files changed, 109 insertions(+) > > create mode 100644 events/arm/armv7-krait/events > > create mode 100644 events/arm/armv7-krait/unit_masks > > > > diff --git a/events/Makefile.am b/events/Makefile.am > > index 3028c2f19ac9..ad45642049dd 100644 > > --- a/events/Makefile.am > > +++ b/events/Makefile.am > > @@ -53,6 +53,7 @@ event_files = \ > > arm/armv7/events arm/armv7/unit_masks \ > > arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ > > arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ > > + arm/armv7-krait/events arm/armv7-krait/unit_masks \ > > arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ > > arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ > > arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ > > diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events > > new file mode 100644 > > index 000000000000..a5dd109f35ea > > --- /dev/null > > +++ b/events/arm/armv7-krait/events > > @@ -0,0 +1,94 @@ > > +# ARM V7 events > > +# From Krait Processor Family Programmer's Reference Manual (PRM) > > +# WARNING: that is ad-hoc change which should be sync with reference manual > > +include:arm/armv7-common > > + > > +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates > > +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses > > +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses > > +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 > > +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 > > +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed > > +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort > > +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ > > +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ > > +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts > > +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined > > +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC > > +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC > > +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort > > +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check > > +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check > > +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU > > +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU > > +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate > > +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU > > + > > +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles > > +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles > > +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles > > +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles > > +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT > > +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) > > +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) > > +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks > > +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle > > +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks > > +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle > > + > > +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR > > +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates > > +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses > > +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses > > +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses > > +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates > > +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates > > +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses > > +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses > > +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses > > +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses > > +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID > > +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA > > +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all > > +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail > > +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold > > +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op > > +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op > > +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier > > + > > +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_DUAL_CYCLE : Krait VIU dual cycle > > +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_SINGLE_CYCLE : Krait VIU single cycle > > +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAR_STALL_CYCLES : Krait VX pipe WAR cycles > > +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAW_STALL_CYCLES : Krait VX pipe WAW cycles > > +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_RAW_STALL_CYCLES : Krait VX pipe RAW cycles > > +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_LOAD_USE_STALL : Krait VX pipe load use stall > > +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAR_STALL_CYCLES : Krait VS pipe WAR stall cycles > > +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAW_STALL_CYCLES : Krait VS pipe WAW stall cycles > > +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_RAW_STALL_CYCLES : Krait VS pipe RAW stall cycles > > +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_INV_OPERATION : Krait invalid operation exceptions > > +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DIV_BY_ZERO : Krait divide by zero exceptions > > +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VX_PIPE : Krait conditional instruction fail VX pipe > > +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VS_PIPE : Krait conditional instruction fail VS pipe > > +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_OVERFLOW : Krait overflow exceptions > > +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_UNDERFLOW : Krait underflow exceptions > > +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DENORM : Krait denorm exceptions > > + > > +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits > > +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses > > +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits > > +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses > > +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits > > +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses > > +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits > > +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses > > +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits > > +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses > > +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits > > +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses > > +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus > > +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus > > +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes > > +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus > > +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) > > +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus > > +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) > > diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks > > new file mode 100644 > > index 000000000000..422e240d46f1 > > --- /dev/null > > +++ b/events/arm/armv7-krait/unit_masks > > @@ -0,0 +1,5 @@ > > +# ARM V7 PMNC possible unit masks > > +# WARNING: that is ad-hoc change which should be sync with reference manual > > +# > > +name:zero type:mandatory default:0x00 > > + 0x00 No unit mask > > diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c > > index 4bb34b72fb6b..9627882f1b7f 100644 > > --- a/libop/op_cpu_type.c > > +++ b/libop/op_cpu_type.c > > @@ -110,6 +110,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { > > { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, > > { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, > > { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, > > + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, > > { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 }, > > { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 }, > > { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 }, > > diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h > > index 4703fa92cd88..f92eb7b08bc0 100644 > > --- a/libop/op_cpu_type.h > > +++ b/libop/op_cpu_type.h > > @@ -90,6 +90,7 @@ typedef enum { > > CPU_WESTMERE, /* Intel Westmere microarchitecture */ > > CPU_ARM_SCORPION, /**< ARM SCORPION */ > > CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ > > + CPU_ARM_KRAIT, /**< ARM KRAIT */ > > CPU_SANDYBRIDGE, /* Intel Sandy-Bridge microarchitecture */ > > CPU_TILE_TILE64, /**< Tilera TILE64 family */ > > CPU_TILE_TILEPRO, /**< Tilera TILEPro family (Pro64 or Pro36) */ > > diff --git a/libop/op_events.c b/libop/op_events.c > > index 39c710df2b41..358a154d127c 100644 > > --- a/libop/op_events.c > > +++ b/libop/op_events.c > > @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) > > case CPU_AVR32: > > case CPU_ARM_SCORPION: > > case CPU_ARM_SCORPIONMP: > > + case CPU_ARM_KRAIT: > > descr->name = "CPU_CYCLES"; > > break; > > > > diff --git a/utils/ophelp.c b/utils/ophelp.c > > index 7543c6f37b7b..01b5ca4f9409 100644 > > --- a/utils/ophelp.c > > +++ b/utils/ophelp.c > > @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) > > "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; > > break; > > > > + case CPU_ARM_KRAIT: > > + event_doc = > > + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" > > + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; > > + break; > > + > > case CPU_ARM_V7_CA9: > > event_doc = > > "See Cortex-A9 Technical Reference Manual\n" > > > > |
From: Stephen B. <sb...@co...> - 2013-11-28 01:44:26
|
On 11/27/13 10:12, Will Deacon wrote: > On Mon, Nov 25, 2013 at 06:57:50PM +0000, Maynard Johnson wrote: >> Hi, Leonid, >> Thanks for the patch. *Will* is the ARM sub-maintainer for oprofile, so I'll have him review it. But a quick look reveals one issue . . . the new CPU type (in op_cpu_type.h) and corresponding description (in op_cpu_type.c) *must* be placed at the end of their respective list. Also, please run 'make distcheck' and verify it passes. > I also don't have any documentation for Krait, but I would be surprised if > simply copying the event encodings over from Snapdragon was the correct > thing to do. > > Rather than run the risk of producing potentially confusing profiling > numbers, I'd really rather we had somebody from Qualcomm rubber-stamp this > patch before we take it any further. > > Adding Stephen Boyd, in case he can help us. Sorry I don't have a rubber stamp for you. All those event encodings are specifically for Scorpion. Take a look at this patch[1] and if you wrap your head around all of it you'll see that the event code region that is "implementation defined" is being re-purposed to index into an array that gives us the arm event code (last column of scorpion_event[]) and some other bits to program into other cp15 registers. A similar hardware scheme exists on Krait but we never wrote the code to map the event encoding in the implementation defined region into the arm event code. Instead we just left it up to userspace to pack that information into the event code and then the kernel driver will unpack the code and figure out what arm event code to program and what other bits to program into the cp15 registers[2]. Now all of this doesn't really matter if you just care about the common PMU event codes that are mandated by ARM. It looks like in your test you're just getting CPU cycles which is going to "just work". Perhaps you can drop all the krait specific event codes from 0x4c to 0xa0 in your patch and just use the common ones for now? [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-March/045306.html [2] https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm_krait.c?id=refs/heads/msm-3.4 > > Will > >> On 11/19/2013 03:37 AM, Leonid Moiseichuk wrote: >>> It is done as a copy of Scorpion CPU due to I have no documentation. >>> Thus corner cases like L2CC PMU might not work but basic set we need >>> is suppored. The opreport output from Krait-based device looks realisic: >>> >>> CPU: ARMv7 Krait, speed 2.2656e+06 MHz (estimated) >>> Counted CPU_CYCLES events (Number of CPU cycles) with a unit mask of 0x00 >>> (No unit mask) count 100000 >>> CPU_CYCLES:100000| >>> samples| %| >>> ------------------ >>> 452276 42.5950 no-vmlinux >>> 312804 29.4596 video-screen >>> CPU_CYCLES:100000| >>> samples| %| >>> ------------------ >>> 116443 37.2255 libpthread-2.13.so >>> 90191 28.8331 libglib-2.0.so.0.3200.3 >>> 33572 10.7326 libecore.so.1.7.99 >>> 32668 10.4436 libc-2.13.so >>> 14625 4.6755 libdbus-1.so.3.7.2 >>> .... >>> >>> Signed-off-by: Leonid Moiseichuk <l.m...@sa...> >>> --- >>> events/Makefile.am | 1 + >>> events/arm/armv7-krait/events | 94 +++++++++++++++++++++++++++++++++++++++ >>> events/arm/armv7-krait/unit_masks | 5 +++ >>> libop/op_cpu_type.c | 1 + >>> libop/op_cpu_type.h | 1 + >>> libop/op_events.c | 1 + >>> utils/ophelp.c | 6 +++ >>> 7 files changed, 109 insertions(+) >>> create mode 100644 events/arm/armv7-krait/events >>> create mode 100644 events/arm/armv7-krait/unit_masks >>> >>> diff --git a/events/Makefile.am b/events/Makefile.am >>> index 3028c2f19ac9..ad45642049dd 100644 >>> --- a/events/Makefile.am >>> +++ b/events/Makefile.am >>> @@ -53,6 +53,7 @@ event_files = \ >>> arm/armv7/events arm/armv7/unit_masks \ >>> arm/armv7-scorpion/events arm/armv7-scorpion/unit_masks \ >>> arm/armv7-scorpionmp/events arm/armv7-scorpionmp/unit_masks \ >>> + arm/armv7-krait/events arm/armv7-krait/unit_masks \ >>> arm/armv7-ca9/events arm/armv7-ca9/unit_masks \ >>> arm/armv7-ca5/events arm/armv7-ca5/unit_masks \ >>> arm/armv7-ca7/events arm/armv7-ca7/unit_masks \ >>> diff --git a/events/arm/armv7-krait/events b/events/arm/armv7-krait/events >>> new file mode 100644 >>> index 000000000000..a5dd109f35ea >>> --- /dev/null >>> +++ b/events/arm/armv7-krait/events >>> @@ -0,0 +1,94 @@ >>> +# ARM V7 events >>> +# From Krait Processor Family Programmer's Reference Manual (PRM) >>> +# WARNING: that is ad-hoc change which should be sync with reference manual >>> +include:arm/armv7-common >>> + >>> +event:0x4c counters:1,2,3,4 um:zero minimum:500 name:ICACHE_EXPL_INV : I-cache explicit invalidates >>> +event:0x4d counters:1,2,3,4 um:zero minimum:500 name:ICACHE_MISS : I-cache misses >>> +event:0x4e counters:1,2,3,4 um:zero minimum:500 name:ICACHE_ACCESS : I-cache accesses >>> +event:0x4f counters:1,2,3,4 um:zero minimum:500 name:ICACHE_CACHEREQ_L2 : I-cache cacheable requests to L2 >>> +event:0x50 counters:1,2,3,4 um:zero minimum:500 name:ICACHE_NOCACHE_L2 : I-cache non-cacheable requests to L2 >>> +event:0x51 counters:1,2,3,4 um:zero minimum:500 name:HIQUP_NOPED : Conditional instructions HIQUPs NOPed >>> +event:0x52 counters:1,2,3,4 um:zero minimum:500 name:DATA_ABORT : Interrupts and Exceptions Data Abort >>> +event:0x53 counters:1,2,3,4 um:zero minimum:500 name:IRQ : Interrupts and Exceptions IRQ >>> +event:0x54 counters:1,2,3,4 um:zero minimum:500 name:FIQ : Interrupts and Exceptions FIQ >>> +event:0x55 counters:1,2,3,4 um:zero minimum:500 name:ALL_EXCPT : Interrupts and Exceptions All interrupts >>> +event:0x56 counters:1,2,3,4 um:zero minimum:500 name:UNDEF : Interrupts and Exceptions Undefined >>> +event:0x57 counters:1,2,3,4 um:zero minimum:500 name:SVC : Interrupts and Exceptions SVC >>> +event:0x58 counters:1,2,3,4 um:zero minimum:500 name:SMC : Interrupts and Exceptions SMC >>> +event:0x59 counters:1,2,3,4 um:zero minimum:500 name:PREFETCH_ABORT : Interrupts and Exceptions Prefetch Abort >>> +event:0x5a counters:1,2,3,4 um:zero minimum:500 name:INDEX_CHECK : Interrupts and Exceptions Index Check >>> +event:0x5b counters:1,2,3,4 um:zero minimum:500 name:NULL_CHECK : Interrupts and Exceptions Null Check >>> +event:0x5c counters:1,2,3,4 um:zero minimum:500 name:EXPL_ICIALLU : I-cache and BTAC Invalidates Explicit ICIALLU >>> +event:0x5d counters:1,2,3,4 um:zero minimum:500 name:IMPL_ICIALLU : I-cache and BTAC Invalidates Implicit ICIALLU >>> +event:0x5e counters:1,2,3,4 um:zero minimum:500 name:NONICIALLU_BTAC_INV : I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate >>> +event:0x5f counters:1,2,3,4 um:zero minimum:500 name:ICIMVAU_IMPL_ICIALLU : I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU >>> + >>> +event:0x60 counters:1,2,3,4 um:zero minimum:500 name:SPIPE_ONLY_CYCLES : Issue S-pipe only issue cycles >>> +event:0x61 counters:1,2,3,4 um:zero minimum:500 name:XPIPE_ONLY_CYCLES : Issue X-pipe only issue cycles >>> +event:0x62 counters:1,2,3,4 um:zero minimum:500 name:DUAL_CYCLES : Issue dual issue cycles >>> +event:0x63 counters:1,2,3,4 um:zero minimum:500 name:DISPATCH_ANY_CYCLES : Dispatch any dispatch cycles >>> +event:0x64 counters:1,2,3,4 um:zero minimum:500 name:FIFO_FULLBLK_CMT : Commits Trace FIFO full Blk CMT >>> +event:0x65 counters:1,2,3,4 um:zero minimum:500 name:FAIL_COND_INST : Conditional instructions failing conditional instrs (excluding branches) >>> +event:0x66 counters:1,2,3,4 um:zero minimum:500 name:PASS_COND_INST : Conditional instructions passing conditional instrs (excluding branches) >>> +event:0x67 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_VU_CLK : Unit Clock Gating Allow VU Clks >>> +event:0x68 counters:1,2,3,4 um:zero minimum:500 name:VU_IDLE : Unit Clock Gating VU Idle >>> +event:0x69 counters:1,2,3,4 um:zero minimum:500 name:ALLOW_L2_CLK : Unit Clock Gating Allow L2 Clks >>> +event:0x6a counters:1,2,3,4 um:zero minimum:500 name:L2_IDLE : Unit Clock Gating L2 Idle >>> + >>> +event:0x6b counters:1,2,3,4 um:zero minimum:500 name:DTLB_IMPL_INV_SCTLR_DACR : DTLB implicit invalidates writes to SCTLR and DACR >>> +event:0x6c counters:1,2,3,4 um:zero minimum:500 name:DTLB_EXPL_INV : DTLB explicit invalidates >>> +event:0x6d counters:1,2,3,4 um:zero minimum:500 name:DTLB_MISS : DTLB misses >>> +event:0x6e counters:1,2,3,4 um:zero minimum:500 name:DTLB_ACCESS : DTLB accesses >>> +event:0x6f counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : ITLB misses >>> +event:0x70 counters:1,2,3,4 um:zero minimum:500 name:ITLB_IMPL_INV : ITLB implicit ITLB invalidates >>> +event:0x71 counters:1,2,3,4 um:zero minimum:500 name:ITLB_EXPL_INV : ITLB explicit ITLB invalidates >>> +event:0x72 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_MISS : UTLB d-side misses >>> +event:0x73 counters:1,2,3,4 um:zero minimum:500 name:UTLB_D_ACCESS : UTLB d-side accesses >>> +event:0x74 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_MISS : UTLB i-side misses >>> +event:0x75 counters:1,2,3,4 um:zero minimum:500 name:UTLB_I_ACCESS : UTLB i-side accesses >>> +event:0x76 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ASID : UTLB invalidate by ASID >>> +event:0x77 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_MVA : UTLB invalidate by MVA >>> +event:0x78 counters:1,2,3,4 um:zero minimum:500 name:UTLB_INV_ALL : UTLB invalidate all >>> +event:0x79 counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_RDQ_UNAVAIL : S2 hold RDQ unavail >>> +event:0x7a counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD : S2 hold S2 hold >>> +event:0x7b counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_DEV_OP : S2 hold device op >>> +event:0x7c counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_ORDER : S2 hold strongly ordered op >>> +event:0x7d counters:1,2,3,4 um:zero minimum:500 name:S2_HOLD_BARRIER : S2 hold barrier >>> + >>> +event:0x7e counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_DUAL_CYCLE : Krait VIU dual cycle >>> +event:0x7f counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VIU_SINGLE_CYCLE : Krait VIU single cycle >>> +event:0x80 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAR_STALL_CYCLES : Krait VX pipe WAR cycles >>> +event:0x81 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_WAW_STALL_CYCLES : Krait VX pipe WAW cycles >>> +event:0x82 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_RAW_STALL_CYCLES : Krait VX pipe RAW cycles >>> +event:0x83 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VX_PIPE_LOAD_USE_STALL : Krait VX pipe load use stall >>> +event:0x84 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAR_STALL_CYCLES : Krait VS pipe WAR stall cycles >>> +event:0x85 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_WAW_STALL_CYCLES : Krait VS pipe WAW stall cycles >>> +event:0x86 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_VS_PIPE_RAW_STALL_CYCLES : Krait VS pipe RAW stall cycles >>> +event:0x87 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_INV_OPERATION : Krait invalid operation exceptions >>> +event:0x88 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DIV_BY_ZERO : Krait divide by zero exceptions >>> +event:0x89 counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VX_PIPE : Krait conditional instruction fail VX pipe >>> +event:0x8a counters:1,2,3,4 um:zero minimum:500 name:KRAIT_COND_INST_FAIL_VS_PIPE : Krait conditional instruction fail VS pipe >>> +event:0x8b counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_OVERFLOW : Krait overflow exceptions >>> +event:0x8c counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_UNDERFLOW : Krait underflow exceptions >>> +event:0x8d counters:1,2,3,4 um:zero minimum:500 name:KRAIT_EXCEPTIONS_DENORM : Krait denorm exceptions >>> + >>> +event:0x8e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_HIT : L2 hit rates bank A/B hits >>> +event:0x8f counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ACCESS : L2 hit rates bank A/B accesses >>> +event:0x90 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_HIT : L2 hit rates bank C/D hits >>> +event:0x91 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ACCESS : L2 hit rates bank C/D accesses >>> +event:0x92 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_HIT : L2 hit rates bank A/B d-side hits >>> +event:0x93 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_DSIDE_ACCESS : L2 hit rates bank A/B d-side accesses >>> +event:0x94 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_HIT : L2 hit rates bank C/D d-side hits >>> +event:0x95 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_DSIDE_ACCESS : L2 hit rates bank C/D d-side accesses >>> +event:0x96 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_HIT : L2 hit rates bank A/B i-side hits >>> +event:0x97 counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_ISIDE_ACCESS : L2 hit rates bank A/B i-side accesses >>> +event:0x98 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_HIT : L2 hit rates bank C/D i-side hits >>> +event:0x99 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_ISIDE_ACCESS : L2 hit rates bank C/D i-side accesses >>> +event:0x9a counters:1,2,3,4 um:zero minimum:500 name:ISIDE_RD_WAIT : fills and castouts cycles that i-side RD requests wait on data from bus >>> +event:0x9b counters:1,2,3,4 um:zero minimum:500 name:DSIDE_RD_WAIT : fills and castouts cycles that d-side RD requests wait on data from bus >>> +event:0x9c counters:1,2,3,4 um:zero minimum:500 name:BANK_BYPASS_WRITE : fills and castouts bank bypass writes >>> +event:0x9d counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_NON_CASTOUT : fills and castouts bank A/B non-castout writes to bus >>> +event:0x9e counters:1,2,3,4 um:zero minimum:500 name:BANK_AB_L2_CASTOUT : fills and castouts bank A/B L2 castouts (granules) >>> +event:0x9f counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_NON_CASTOUT : fills and castouts bank C/D non-castout writes to bus >>> +event:0xa0 counters:1,2,3,4 um:zero minimum:500 name:BANK_CD_L2_CASTOUT : fills and castouts bank C/D L2 castouts (granules) >>> diff --git a/events/arm/armv7-krait/unit_masks b/events/arm/armv7-krait/unit_masks >>> new file mode 100644 >>> index 000000000000..422e240d46f1 >>> --- /dev/null >>> +++ b/events/arm/armv7-krait/unit_masks >>> @@ -0,0 +1,5 @@ >>> +# ARM V7 PMNC possible unit masks >>> +# WARNING: that is ad-hoc change which should be sync with reference manual >>> +# >>> +name:zero type:mandatory default:0x00 >>> + 0x00 No unit mask >>> diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c >>> index 4bb34b72fb6b..9627882f1b7f 100644 >>> --- a/libop/op_cpu_type.c >>> +++ b/libop/op_cpu_type.c >>> @@ -110,6 +110,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { >>> { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, >>> { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, >>> { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, >>> + { "ARMv7 Krait", "arm/armv7-krait", CPU_ARM_KRAIT, 5 }, >>> { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 }, >>> { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 }, >>> { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 }, >>> diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h >>> index 4703fa92cd88..f92eb7b08bc0 100644 >>> --- a/libop/op_cpu_type.h >>> +++ b/libop/op_cpu_type.h >>> @@ -90,6 +90,7 @@ typedef enum { >>> CPU_WESTMERE, /* Intel Westmere microarchitecture */ >>> CPU_ARM_SCORPION, /**< ARM SCORPION */ >>> CPU_ARM_SCORPIONMP, /**< ARM SCORPIONMP */ >>> + CPU_ARM_KRAIT, /**< ARM KRAIT */ >>> CPU_SANDYBRIDGE, /* Intel Sandy-Bridge microarchitecture */ >>> CPU_TILE_TILE64, /**< Tilera TILE64 family */ >>> CPU_TILE_TILEPRO, /**< Tilera TILEPro family (Pro64 or Pro36) */ >>> diff --git a/libop/op_events.c b/libop/op_events.c >>> index 39c710df2b41..358a154d127c 100644 >>> --- a/libop/op_events.c >>> +++ b/libop/op_events.c >>> @@ -1252,6 +1252,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) >>> case CPU_AVR32: >>> case CPU_ARM_SCORPION: >>> case CPU_ARM_SCORPIONMP: >>> + case CPU_ARM_KRAIT: >>> descr->name = "CPU_CYCLES"; >>> break; >>> >>> diff --git a/utils/ophelp.c b/utils/ophelp.c >>> index 7543c6f37b7b..01b5ca4f9409 100644 >>> --- a/utils/ophelp.c >>> +++ b/utils/ophelp.c >>> @@ -622,6 +622,12 @@ int main(int argc, char const * argv[]) >>> "Scorpion Processor Family Programmer's Reference Manual (PRM)\n"; >>> break; >>> >>> + case CPU_ARM_KRAIT: >>> + event_doc = >>> + "See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition\n" >>> + "Krait Processor Family Programmer's Reference Manual (PRM)\n"; >>> + break; >>> + >>> case CPU_ARM_V7_CA9: >>> event_doc = >>> "See Cortex-A9 Technical Reference Manual\n" >>> >> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation |
From: Leonid M. <l.m...@sa...> - 2013-12-10 13:47:08
|
Hi, > -----Original Message----- > From: Stephen Boyd [mailto:sb...@co...] ... > Instead we just left it up to userspace to pack that information into > the event code and then the kernel driver will unpack the code and > figure out what arm event code to program and what other bits to > program into the cp15 registers[2]. > > Now all of this doesn't really matter if you just care about the common > PMU event codes that are mandated by ARM. It looks like in your test > you're just getting CPU cycles which is going to "just work". Perhaps > you can drop all the krait specific event codes from 0x4c to 0xa0 in > your patch and just use the common ones for now? > > [1] > http://lists.infradead.org/pipermail/linux-arm-kernel/2011- > March/045306.html > [2] > https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel > /perf_event_msm_krait.c?id=refs/heads/msm-3.4 > ... Thanks for advice, I implemented what do you propose in v3 of patch. operf also works fine after that. Best Wishes, Leonid |