Intel 1GHz
linux 2.4.9
freeswan-1.98b
crytpolib patch.
My system can run ipsec 3des+md5 in tuunel mode at around 22Mbit/sec. But after some time, the hardware card just stops. I dump the registers
on the card after the card stop working.
Feb 18 19:51:23 cpu control: 00000000
Feb 18 19:51:23 cpu int status: 000030f4
Feb 18 19:51:23 cpu conf: 00000340
Feb 18 19:51:23 cpu int enable: 00008000
Feb 18 19:51:23 cpu status: 00002090
Feb 18 19:51:23 fifo status: 00004000
Feb 18 19:51:23 fifo conf: 00000400
Feb 18 19:51:23
Feb 18 19:51:23 command ring: 00fcb00c
Feb 18 19:51:23 source ring: 00fcb024
Feb 18 19:51:23 result ring: 00fcb034
Feb 18 19:51:23 dest ring: 00fcb044
Feb 18 19:51:23 dma status control: 80888084
Feb 18 19:51:23 dma int enable: 20302020
Feb 18 19:51:23 dma conf: 00100317
Feb 18 19:51:23 dma chipid: 00120000
Any idea? Thanks.
Jacky
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
After struggling in the data sheet and the source code, I guess the problem is the value set into dma interrupt enable register. The register is written with RESRING_DONE. For 3DES+MD5, there are 2 interrupts generated to complete the encryption/decryption. Somehow, the chip stops interrupting. As shown on the register dump, the RESRING bit was not set on dma status register. But the LAST bit was set. After further inspect the register, I decide to use RESRING_LAST instead of RESING_DONE. The interrupt number is reduced by half and it's working fine for now.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
My system is
Intel 1GHz
linux 2.4.9
freeswan-1.98b
crytpolib patch.
My system can run ipsec 3des+md5 in tuunel mode at around 22Mbit/sec. But after some time, the hardware card just stops. I dump the registers
on the card after the card stop working.
Feb 18 19:51:23 cpu control: 00000000
Feb 18 19:51:23 cpu int status: 000030f4
Feb 18 19:51:23 cpu conf: 00000340
Feb 18 19:51:23 cpu int enable: 00008000
Feb 18 19:51:23 cpu status: 00002090
Feb 18 19:51:23 fifo status: 00004000
Feb 18 19:51:23 fifo conf: 00000400
Feb 18 19:51:23
Feb 18 19:51:23 command ring: 00fcb00c
Feb 18 19:51:23 source ring: 00fcb024
Feb 18 19:51:23 result ring: 00fcb034
Feb 18 19:51:23 dest ring: 00fcb044
Feb 18 19:51:23 dma status control: 80888084
Feb 18 19:51:23 dma int enable: 20302020
Feb 18 19:51:23 dma conf: 00100317
Feb 18 19:51:23 dma chipid: 00120000
Any idea? Thanks.
Jacky
After struggling in the data sheet and the source code, I guess the problem is the value set into dma interrupt enable register. The register is written with RESRING_DONE. For 3DES+MD5, there are 2 interrupts generated to complete the encryption/decryption. Somehow, the chip stops interrupting. As shown on the register dump, the RESRING bit was not set on dma status register. But the LAST bit was set. After further inspect the register, I decide to use RESRING_LAST instead of RESING_DONE. The interrupt number is reduced by half and it's working fine for now.