From: Jozsef L. <len...@gm...> - 2007-10-15 14:29:20
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Hi, I've managed the Sony ACX705AKM display to work, but i have a little color problem. The dark (black or dark blue) regions of the image are green. My own code that displays images is based on the ppmv_sony692. The problem occurs with the ppmv_sony692 too, for example the darker regions of the sony_penguin,ppm are green. Any idea ? Is this a hw (maybe wiring) or sw (color format) problem ? Thanks, Jocc |
From: Jozsef L. <len...@gm...> - 2007-10-15 15:31:11
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Hi, i'm using verdex and the display is in 16bit mode, i've done the register settings below, but nothing changed. 2007/10/15, Jay Snyder <jay...@ty...>: > What Gumstix motherboard are you using? Verdex, Connex or Basix? > > If you are using a Verdex motherboard, and a 16 bit display, you'll need > to set the pixel format to 16 bit: > > I used the following to do that: > pxaregs LCCR3_PDFOR 0 > pxaregs LCCR4_PAL_FOR 0 > Thanks, Jocc |
From: Jay S. <jay...@ty...> - 2007-10-15 15:37:29
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Do you have the modified pxaregs? The stock pxaregs that comes with the gumstix distro won't work, as it doesn't support these regs. pxaregs.c was written for the PXA255 (used on the connex and basix), I have added some (but not all) of the PXA270's new registers to it. see my modified version here: http://gdx.dynalias.com/gumstix/pxaregs.c Jozsef Lenart wrote: > > Hi, > > i'm using verdex and the display is in 16bit mode, i've done the > register settings below, but nothing changed. > > 2007/10/15, Jay Snyder <jay...@ty...>: > > What Gumstix motherboard are you using? Verdex, Connex or Basix? > > > > If you are using a Verdex motherboard, and a 16 bit display, you'll > need > > to set the pixel format to 16 bit: > > > > I used the following to do that: > > pxaregs LCCR3_PDFOR 0 > > pxaregs LCCR4_PAL_FOR 0 > > > > Thanks, > Jocc > |
From: Jay S. <jay...@ty...> - 2007-10-15 16:24:19
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I set all the other regs from /etc/modules: pxafb options=mode:240x320-16,active,hsynclen:100,vsynclen:1,left:10,right:0,upper:5,lower:2,pixclock:183000,hsync:1,vsync:1,outputen:1,pixclockpol:0 I didn't bother with LCCR0_ENB, as I probably didn't read thoroughly enough to see that. It is possible that when you disable and re-enable the display, you need to re-set all the other regs. Regards, Jay Jozsef Lenart wrote: > > Hi, > > yes i'm using the modified pxaregs. > I've seen at the pxa270 developer's manual, that i should disable the > LCD controller (LCCR0_ENB 0) when i change the values of LCCR3. But > when i disable the controller, change LCCR3_PDFOR (and LCCR4_PAL_FOR), > then i re-enable the controller, the image dims, and don't gets back > after "pxaregs LCCR0_ENB 1", it remains blank. I set the other > (timing) regs in the u-boot bootargs, according to the GumstixDocsWiki > (http://docwiki.gumstix.org/Display#Setting_the_LCCR_registers_from_Kernel) > > > Thanks, > Jocc > |
From: Jozsef L. <len...@gm...> - 2007-10-15 16:48:54
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Hi, it seems that i have problems only with the blue component. Where there are much dark blue pixels on the image, the display shows green. Other colors are correct. I checked the pixel format of the framebuffer, and it seems to be 2 byte per pixel RRR00GGG000BBB00 (5 6 5 alignment). The bit-shifting maneuvers in the ppmv_sony692 shows this too. Is it correct ? Jocc 2007/10/15, Jay Snyder <jay...@ty...>: > > I set all the other regs from /etc/modules: > pxafb > options=mode:240x320-16,active,hsynclen:100,vsynclen:1,left:10,right:0,upper:5,lower:2,pixclock:183000,hsync:1,vsync:1,outputen:1,pixclockpol:0 > > I didn't bother with LCCR0_ENB, as I probably didn't read thoroughly enough > to see that. > It is possible that when you disable and re-enable the display, you need to > re-set all the other regs. > > Regards, > Jay |
From: Jozsef L. <len...@gm...> - 2007-10-18 10:27:10
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Hi, i still have the problem with the colors. I have no more ideas. I've debugged the problem few days, but this is totally screwed. Let's see the sony_penguin2.ppm image. It has some gray blobs on the head, on the side of the penguin and on the belly. Where the gray is on a black background (eg. on the head) the gray goes to be green on the display. But where the gray is on white surface it remains gray on the display. I suspected some bit-shifting problem, but after this test... i have no idea. (verdex xm4, breakout-vx, sony acx705akm, bootargs according to the docswiki (240x160-16)) Regards, Jocc |
From: Craig H. <cr...@gu...> - 2007-10-18 15:43:37
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On Oct 18, 2007, at 3:27 AM, Jozsef Lenart wrote: > i still have the problem with the colors. I have no more ideas. I've > debugged the problem few days, but this is totally screwed. > Let's see the sony_penguin2.ppm image. It has some gray blobs on the > head, on the side of the penguin and on the belly. Where the gray is > on a black background (eg. on the head) the gray goes to be green on > the display. But where the gray is on white surface it remains gray on > the display. > I suspected some bit-shifting problem, but after this test... i > have no idea. > (verdex xm4, breakout-vx, sony acx705akm, bootargs according to the > docswiki (240x160-16)) What is the output of "pxaregs LCCR"? C |
From: Jozsef L. <len...@gm...> - 2007-10-20 10:03:46
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Hi, The output of "pxaregs LCCR*" : LCD Controller Control Register 0 (7-23) LCCR0 0x003008f9 00000000 00110000 00001000 11111001 LCCR0_ENB 1 LCD controller enable LCCR0_CMS 0 LCD monochrome operation enable LCCR0_SDS 0 LCD dual panel display enable LCCR0_LDM 1 LCD disable done IRQ disable LCCR0_SFM 1 LCD start of frame IRQ disable LCCR0_IUM 1 LCD fifo underrun error IRQ disable LCCR0_EFM 1 LCD end of frame IRQ disable LCCR0_PAS 1 LCD active display enable LCCR0_DPD 0 LCD send 8 pixel on L_DD[7:0] at each clock LCCR0_DIS 0 LCD controller disable LCCR0_QDM 1 LCD quick disable IRQ disable LCCR0_PDD 0 LCD palette DMA request delay LCCR0_BM 1 LCD branch start IRQ disable LCCR0_OUM 1 LCD fifo underrun IRQ disable LCD Controller Control Register 1 (7-26) LCCR1 0x040f18ef 00000100 00001111 00011000 11101111 LCCR1_PPL 239 LCD pixels per line (+1) LCCR1_HSW 6 LCD horizontal sync pulse width (+1) LCCR1_ELW 15 LCD end of line pixel clock wait count (+1) LCCR1_BLW 4 LCD beginning of line pixel clock wait cou) LCD Controller Control Register 2 (7-28) LCCR2 0x1313049f 00010011 00010011 00000100 10011111 LCCR2_LPP 159 LCD lines per panel (+1) LCCR2_VSW 1 LCD vertical sync pulse width (+1) LCCR2_EFW 19 LCD end of frame line clock wait count (+1) LCCR2_BFW 19 LCD beginning of frame line clock wait cou) LCD Controller Control Register 3 (7-31) LCCR3 0x04400004 00000100 01000000 00000000 00000100 LCCR3_PCD 4 LCD pixel clock divisor (+1) LCCR3_ACB 0 LCD AC bias pin frequency (+1) LCCR3_API 0 LCD AC bias pin transitions per interrupt LCCR3_VSP 0 LCD L_FCLK vertical sync polarity active lw LCCR3_HSP 0 LCD L_LCLK horizontal sync polarity activew LCCR3_PCP 1 LCD data sampled on falling edge of L_PCLK LCCR3_OEP 0 LCD L_BIAS output enable active low LCCR3_BPP 16 LCD bits per pixel LCCR3_DPC 0 LCD double pixel clock rate at L_PCLK LCCR3_BPP3 0 LCD bits per pixel LCCR3_PDFOR 0 Pixel Data Format LCD Controller Control Register 4 (PXA270) LCCR4 0x00000000 00000000 00000000 00000000 00000000 LCCR4_K1 0 LCD K1 Multiplication Constrant for Red hay LCCR4_K2 0 LCD K2 Multiplication Constrant for Blue hy LCCR4_K3 0 LCD K3 Multiplication Constrant for Green y LCCR4_PAL_FOR 0 LCD PAL_FOR LCCR4_PCDDIV 0 LCD PCD Divisor Selector Regards, Jocc |