From: Reid L. <lr...@cs...> - 2008-03-15 16:00:38
Attachments:
r300_artifact.gif
r300_artifact_pure.gif
|
Hi list, this is my first time posting and I'm not subscribed. I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. Some time ago I noticed that seemingly random pixels were not being rendered in all GL contexts, and simply chalked it up to my card aging. But after a while it started to irk me, and then I remembered something about my sapphire 9500 - it's got one of the chips with 8 pipelines but only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged as a 9500. At one time this card was on a Windows box, and I tried enabling all 8 pipelines with the softmod, and got the checkerboard pattern that indicated this. With this in mind, I took 10 dumps of a glxgears window and merged them together in a multilayer image in gimp, alternating multiply/divide, and overlaid a 16x16 grid. The artifacting lined up perfectly in the checkerboard pattern. I'm now pretty convinced that somehow either my system's DRM module, DRI, or radeon driver are erroneously enabling all 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have any thoughts on this? I've attached the images with and without the overlaid grid for reference. |
From: Reid L. <lr...@cs...> - 2008-03-15 16:01:23
|
Reid Linnemann wrote: > Hi list, this is my first time posting and I'm not subscribed. > Correction, I have subscribed =) |
From: Jerome G. <gl...@fr...> - 2008-03-16 23:55:47
|
On Sat, 15 Mar 2008 11:00:25 -0500 Reid Linnemann <lr...@cs...> wrote: > Hi list, this is my first time posting and I'm not subscribed. > > I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > > Some time ago I noticed that seemingly random pixels were not being > rendered in all GL contexts, and simply chalked it up to my card aging. > But after a while it started to irk me, and then I remembered something > about my sapphire 9500 - it's got one of the chips with 8 pipelines but > only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > as a 9500. At one time this card was on a Windows box, and I tried > enabling all 8 pipelines with the softmod, and got the checkerboard > pattern that indicated this. > > With this in mind, I took 10 dumps of a glxgears window and merged them > together in a multilayer image in gimp, alternating multiply/divide, and > overlaid a 16x16 grid. The artifacting lined up perfectly in the > checkerboard pattern. I'm now pretty convinced that somehow either my > system's DRM module, DRI, or radeon driver are erroneously enabling all > 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > any thoughts on this? > > I've attached the images with and without the overlaid grid for reference. > > >From memory code which detect card model and decide how many pipe to enable is wrong for many card. We were just optimistic. Cheers, Jerome Glisse <gl...@fr...> |
From: Alex D. <ale...@gm...> - 2008-03-17 00:48:03
|
On Sun, Mar 16, 2008 at 7:55 PM, Jerome Glisse <gl...@fr...> wrote: > > On Sat, 15 Mar 2008 11:00:25 -0500 > Reid Linnemann <lr...@cs...> wrote: > > > Hi list, this is my first time posting and I'm not subscribed. > > > > I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > > > > Some time ago I noticed that seemingly random pixels were not being > > rendered in all GL contexts, and simply chalked it up to my card aging. > > But after a while it started to irk me, and then I remembered something > > about my sapphire 9500 - it's got one of the chips with 8 pipelines but > > only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > > as a 9500. At one time this card was on a Windows box, and I tried > > enabling all 8 pipelines with the softmod, and got the checkerboard > > pattern that indicated this. > > > > With this in mind, I took 10 dumps of a glxgears window and merged them > > together in a multilayer image in gimp, alternating multiply/divide, and > > overlaid a 16x16 grid. The artifacting lined up perfectly in the > > checkerboard pattern. I'm now pretty convinced that somehow either my > > system's DRM module, DRI, or radeon driver are erroneously enabling all > > 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > > any thoughts on this? > > > > I've attached the images with and without the overlaid grid for reference. > > > > > > >From memory code which detect card model and decide how many > pipe to enable is wrong for many card. We were just optimistic. > There is a way to detect bad pipes and the proper number of pipes to enable per-card, but It hasn't been implemented yet. I'll try and dig up what we need. Alex |
From: Reid L. <lr...@cs...> - 2008-03-17 00:50:09
|
Jerome Glisse wrote: > On Sat, 15 Mar 2008 11:00:25 -0500 > Reid Linnemann <lr...@cs...> wrote: > >> Hi list, this is my first time posting and I'm not subscribed. >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >> >> Some time ago I noticed that seemingly random pixels were not being >> rendered in all GL contexts, and simply chalked it up to my card aging. >> But after a while it started to irk me, and then I remembered something >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >> as a 9500. At one time this card was on a Windows box, and I tried >> enabling all 8 pipelines with the softmod, and got the checkerboard >> pattern that indicated this. >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >> together in a multilayer image in gimp, alternating multiply/divide, and >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >> checkerboard pattern. I'm now pretty convinced that somehow either my >> system's DRM module, DRI, or radeon driver are erroneously enabling all >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >> any thoughts on this? >> >> I've attached the images with and without the overlaid grid for reference. >> >> > >>From memory code which detect card model and decide how many > pipe to enable is wrong for many card. We were just optimistic. > > Cheers, > Jerome Glisse <gl...@fr...> I'd be fine if I knew what code initialized the pipelines, then I might be able to alter it to my needs. |
From: Alex D. <ale...@gm...> - 2008-03-17 00:56:02
|
On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: > Jerome Glisse wrote: > > On Sat, 15 Mar 2008 11:00:25 -0500 > > Reid Linnemann <lr...@cs...> wrote: > > > >> Hi list, this is my first time posting and I'm not subscribed. > >> > >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > >> > >> Some time ago I noticed that seemingly random pixels were not being > >> rendered in all GL contexts, and simply chalked it up to my card aging. > >> But after a while it started to irk me, and then I remembered something > >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but > >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > >> as a 9500. At one time this card was on a Windows box, and I tried > >> enabling all 8 pipelines with the softmod, and got the checkerboard > >> pattern that indicated this. > >> > >> With this in mind, I took 10 dumps of a glxgears window and merged them > >> together in a multilayer image in gimp, alternating multiply/divide, and > >> overlaid a 16x16 grid. The artifacting lined up perfectly in the > >> checkerboard pattern. I'm now pretty convinced that somehow either my > >> system's DRM module, DRI, or radeon driver are erroneously enabling all > >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > >> any thoughts on this? > >> > >> I've attached the images with and without the overlaid grid for reference. > >> > >> > > > >>From memory code which detect card model and decide how many > > pipe to enable is wrong for many card. We were just optimistic. > > > > Cheers, > > Jerome Glisse <gl...@fr...> > > I'd be fine if I knew what code initialized the pipelines, then I might > be able to alter it to my needs. > search for R300_GB_TILE_PIPE_COUNT in r300_state.c Alex |
From: Reid L. <lr...@cs...> - 2008-03-17 13:08:27
|
Written by Alex Deucher on 03/16/08 19:55>> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: >> Jerome Glisse wrote: >> > On Sat, 15 Mar 2008 11:00:25 -0500 >> > Reid Linnemann <lr...@cs...> wrote: >> > >> >> Hi list, this is my first time posting and I'm not subscribed. >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >> >> >> >> Some time ago I noticed that seemingly random pixels were not being >> >> rendered in all GL contexts, and simply chalked it up to my card aging. >> >> But after a while it started to irk me, and then I remembered something >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >> >> as a 9500. At one time this card was on a Windows box, and I tried >> >> enabling all 8 pipelines with the softmod, and got the checkerboard >> >> pattern that indicated this. >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >> >> together in a multilayer image in gimp, alternating multiply/divide, and >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >> >> checkerboard pattern. I'm now pretty convinced that somehow either my >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >> >> any thoughts on this? >> >> >> >> I've attached the images with and without the overlaid grid for reference. >> >> >> >> >> > >> >>From memory code which detect card model and decide how many >> > pipe to enable is wrong for many card. We were just optimistic. >> > >> > Cheers, >> > Jerome Glisse <gl...@fr...> >> >> I'd be fine if I knew what code initialized the pipelines, then I might >> be able to alter it to my needs. >> > > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > > Alex FWIW I've tried changing the value of this constant from 3<<1 (or 6) to 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just appear as flickering holes in the gl context in the same checkerboard pattern. Does that mean anything to you? Thanks, Reid |
From: Alex J. <awj...@ho...> - 2008-03-19 23:29:32
|
> Date: Wed, 19 Mar 2008 18:10:43 -0400 > From: ale...@gm... > To: lr...@cs... > CC: dri...@li... > Subject: Re: [Dri-users] Visual artifacts on radeon 9500 dri > > On Tue, Mar 18, 2008 at 9:45 AM, Reid Linnemann <lr...@cs...> wrote: > > Written by Alex Deucher on 03/18/08 08:39>> > > > > > > > On Tue, Mar 18, 2008 at 9:02 AM, Reid Linnemann <lr...@cs...> wrote: > > >> Written by Alex Deucher on 03/17/08 08:18>> > > >> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: > > >> >> Written by Alex Deucher on 03/16/08 19:55>> > > >> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: > > >> >> >> Jerome Glisse wrote: > > >> >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 > > >> >> >> > Reid Linnemann <lr...@cs...> wrote: > > >> >> >> > > > >> >> >> >> Hi list, this is my first time posting and I'm not subscribed. > > >> >> >> >> > > >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > > >> >> >> >> > > >> >> >> >> Some time ago I noticed that seemingly random pixels were not being > > >> >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. > > >> >> >> >> But after a while it started to irk me, and then I remembered something > > >> >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but > > >> >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > > >> >> >> >> as a 9500. At one time this card was on a Windows box, and I tried > > >> >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard > > >> >> >> >> pattern that indicated this. > > >> >> >> >> > > >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them > > >> >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and > > >> >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the > > >> >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my > > >> >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all > > >> >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > > >> >> >> >> any thoughts on this? > > >> >> >> >> > > >> >> >> >> I've attached the images with and without the overlaid grid for reference. > > >> >> >> >> > > >> >> >> >> > > >> >> >> > > > >> >> >> >>From memory code which detect card model and decide how many > > >> >> >> > pipe to enable is wrong for many card. We were just optimistic. > > >> >> >> > > > >> >> >> > Cheers, > > >> >> >> > Jerome Glisse <gl...@fr...> > > >> >> >> > > >> >> >> I'd be fine if I knew what code initialized the pipelines, then I might > > >> >> >> be able to alter it to my needs. > > >> >> >> > > >> >> > > > >> >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > > >> >> > > > >> >> > Alex > > >> >> > > >> >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to > > >> >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just > > >> >> appear as flickering holes in the gl context in the same checkerboard > > >> >> pattern. Does that mean anything to you? > > >> > > > >> > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 > > >> > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > > >> > documentation for these chips are available here: > > >> > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > > >> > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > > >> > > > >> > In your case I suspect you want 0. > > >> > > > >> > Alex > > >> > > >> That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h > > >> fixed the tiling issue. Huzzah! > > >> > > > > > > Hey, send me your pci ids so I can push the fix upstream. > > > > > > Alex > > > > pciconf -lv output: > > fix pushed to mesa: 65c4ced1ccea7ff88123296b7f0587faa6f23eef Wouldn't it be better, now that we have those register docs, to get the number of working pipes from the card itself (specifically GB_PIPE_SELECT) rather than using a list of PCI ids? --AWJ-- _________________________________________________________________ Turn every day into $1000. Learn more at SignInAndWIN.ca http://g.msn.ca/ca55/213 |
From: Alex D. <ale...@gm...> - 2008-03-19 23:51:59
|
On Wed, Mar 19, 2008 at 7:29 PM, Alex Jackson <awj...@ho...> wrote: > > > Date: Wed, 19 Mar 2008 18:10:43 -0400 > > From: ale...@gm... > > To: lr...@cs... > > CC: dri...@li... > > Subject: Re: [Dri-users] Visual artifacts on radeon 9500 dri > > > > > > On Tue, Mar 18, 2008 at 9:45 AM, Reid Linnemann <lr...@cs...> > wrote: > > > Written by Alex Deucher on 03/18/08 08:39>> > > > > > > > > > > On Tue, Mar 18, 2008 at 9:02 AM, Reid Linnemann <lr...@cs...> > wrote: > > > >> Written by Alex Deucher on 03/17/08 08:18>> > > > >> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann > <lr...@cs...> wrote: > > > >> >> Written by Alex Deucher on 03/16/08 19:55>> > > > >> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann > <lr...@cs...> wrote: > > > >> >> >> Jerome Glisse wrote: > > > >> >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 > > > >> >> >> > Reid Linnemann <lr...@cs...> wrote: > > > >> >> >> > > > > >> >> >> >> Hi list, this is my first time posting and I'm not > subscribed. > > > >> >> >> >> > > > >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > > > >> >> >> >> > > > >> >> >> >> Some time ago I noticed that seemingly random pixels were > not being > > > >> >> >> >> rendered in all GL contexts, and simply chalked it up to my > card aging. > > > >> >> >> >> But after a while it started to irk me, and then I > remembered something > > > >> >> >> >> about my sapphire 9500 - it's got one of the chips with 8 > pipelines but > > > >> >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and > was rebadged > > > >> >> >> >> as a 9500. At one time this card was on a Windows box, and I > tried > > > >> >> >> >> enabling all 8 pipelines with the softmod, and got the > checkerboard > > > >> >> >> >> pattern that indicated this. > > > >> >> >> >> > > > >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and > merged them > > > >> >> >> >> together in a multilayer image in gimp, alternating > multiply/divide, and > > > >> >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in > the > > > >> >> >> >> checkerboard pattern. I'm now pretty convinced that somehow > either my > > > >> >> >> >> system's DRM module, DRI, or radeon driver are erroneously > enabling all > > > >> >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. > Anyone have > > > >> >> >> >> any thoughts on this? > > > >> >> >> >> > > > >> >> >> >> I've attached the images with and without the overlaid grid > for reference. > > > >> >> >> >> > > > >> >> >> >> > > > >> >> >> > > > > >> >> >> >>From memory code which detect card model and decide how many > > > >> >> >> > pipe to enable is wrong for many card. We were just > optimistic. > > > >> >> >> > > > > >> >> >> > Cheers, > > > >> >> >> > Jerome Glisse <gl...@fr...> > > > >> >> >> > > > >> >> >> I'd be fine if I knew what code initialized the pipelines, then > I might > > > >> >> >> be able to alter it to my needs. > > > >> >> >> > > > >> >> > > > > >> >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > > > >> >> > > > > >> >> > Alex > > > >> >> > > > >> >> FWIW I've tried changing the value of this constant from 3<<1 (or > 6) to > > > >> >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They > just > > > >> >> appear as flickering holes in the gl context in the same > checkerboard > > > >> >> pattern. Does that mean anything to you? > > > >> > > > > >> > The only valid values for pipe count (bits 3:1) for r3xx chips are > 0 > > > >> > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > > > >> > documentation for these chips are available here: > > > >> > > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > > > >> > > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > > > >> > > > > >> > In your case I suspect you want 0. > > > >> > > > > >> > Alex > > > >> > > > >> That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h > > > >> fixed the tiling issue. Huzzah! > > > >> > > > > > > > > Hey, send me your pci ids so I can push the fix upstream. > > > > > > > > Alex > > > > > > pciconf -lv output: > > > > fix pushed to mesa: 65c4ced1ccea7ff88123296b7f0587faa6f23eef > > Wouldn't it be better, now that we have those register docs, to get the > number of working pipes from the card itself (specifically GB_PIPE_SELECT) > rather than using a list of PCI ids? Yes, I'm working on it :) However, r3xx chips don't have GB_PIPE_SELECT. Only r4xx, rs4xx and r5xx do. Alex |
From: Alex J. <awj...@ho...> - 2008-03-20 05:41:59
|
> Date: Wed, 19 Mar 2008 19:51:57 -0400 > From: ale...@gm... > To: awj...@ho... > Subject: Re: [Dri-users] Visual artifacts on radeon 9500 dri > CC: lr...@cs...; dri...@li... > > On Wed, Mar 19, 2008 at 7:29 PM, Alex Jackson <awj...@ho...> wrote: > > Wouldn't it be better, now that we have those register docs, to get the > > number of working pipes from the card itself (specifically GB_PIPE_SELECT) > > rather than using a list of PCI ids? > > Yes, I'm working on it :) > However, r3xx chips don't have GB_PIPE_SELECT. Only r4xx, rs4xx and r5xx do. Yeah, I just looked at the newly-dropped R300 doc and noticed that there's no sign of that register. I guess that's why the 9500s were easy to "softmod" in Windows, and there's no choice for those cards but to use a list of PCI IDs... According to the R500 doc, it looks like you can just set GB_PIPE_SELECT to the maximum (16 pipes) on all R4xx and R5xx cards and the card will automatically correct it to the actual number of working pipes. Is this right or am I misinterpreting the doc? I guess we'll want to query the card anyway for the real number of working pipes when/if we start tweaking the bits in GB_TILE_CONFIG for performance like the binary drivers (presumably) do. For example it looks like there's a bit in that register that's specific to 12-pipe configurations, and selects one of two ways of splitting the pixels between the three quads, any idea how that works? Is it something like [1][2] [3] versus [1] [2][3] ?? --AWJ-- _________________________________________________________________ Enter today for your chance to win $1000 a day—today until May 12th. Learn more at SignInAndWIN.ca http://g.msn.ca/ca55/215 |
From: Alex D. <ale...@gm...> - 2008-03-17 13:18:11
|
On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: > Written by Alex Deucher on 03/16/08 19:55>> > > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: > >> Jerome Glisse wrote: > >> > On Sat, 15 Mar 2008 11:00:25 -0500 > >> > Reid Linnemann <lr...@cs...> wrote: > >> > > >> >> Hi list, this is my first time posting and I'm not subscribed. > >> >> > >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > >> >> > >> >> Some time ago I noticed that seemingly random pixels were not being > >> >> rendered in all GL contexts, and simply chalked it up to my card aging. > >> >> But after a while it started to irk me, and then I remembered something > >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but > >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > >> >> as a 9500. At one time this card was on a Windows box, and I tried > >> >> enabling all 8 pipelines with the softmod, and got the checkerboard > >> >> pattern that indicated this. > >> >> > >> >> With this in mind, I took 10 dumps of a glxgears window and merged them > >> >> together in a multilayer image in gimp, alternating multiply/divide, and > >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the > >> >> checkerboard pattern. I'm now pretty convinced that somehow either my > >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all > >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > >> >> any thoughts on this? > >> >> > >> >> I've attached the images with and without the overlaid grid for reference. > >> >> > >> >> > >> > > >> >>From memory code which detect card model and decide how many > >> > pipe to enable is wrong for many card. We were just optimistic. > >> > > >> > Cheers, > >> > Jerome Glisse <gl...@fr...> > >> > >> I'd be fine if I knew what code initialized the pipelines, then I might > >> be able to alter it to my needs. > >> > > > > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > > > > Alex > > FWIW I've tried changing the value of this constant from 3<<1 (or 6) to > 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just > appear as flickering holes in the gl context in the same checkerboard > pattern. Does that mean anything to you? The only valid values for pipe count (bits 3:1) for r3xx chips are 0 (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The documentation for these chips are available here: http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf In your case I suspect you want 0. Alex |
From: Reid L. <lr...@cs...> - 2008-03-17 15:10:42
|
Written by Alex Deucher on 03/17/08 08:18>> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: >> Written by Alex Deucher on 03/16/08 19:55>> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: >> >> Jerome Glisse wrote: >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 >> >> > Reid Linnemann <lr...@cs...> wrote: >> >> > >> >> >> Hi list, this is my first time posting and I'm not subscribed. >> >> >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >> >> >> >> >> >> Some time ago I noticed that seemingly random pixels were not being >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. >> >> >> But after a while it started to irk me, and then I remembered something >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >> >> >> as a 9500. At one time this card was on a Windows box, and I tried >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard >> >> >> pattern that indicated this. >> >> >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >> >> >> any thoughts on this? >> >> >> >> >> >> I've attached the images with and without the overlaid grid for reference. >> >> >> >> >> >> >> >> > >> >> >>From memory code which detect card model and decide how many >> >> > pipe to enable is wrong for many card. We were just optimistic. >> >> > >> >> > Cheers, >> >> > Jerome Glisse <gl...@fr...> >> >> >> >> I'd be fine if I knew what code initialized the pipelines, then I might >> >> be able to alter it to my needs. >> >> >> > >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c >> > >> > Alex >> >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just >> appear as flickering holes in the gl context in the same checkerboard >> pattern. Does that mean anything to you? > > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > documentation for these chips are available here: > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > > In your case I suspect you want 0. > > Alex Ah, I see. I wondered why the tile pipe count constants were specified as left-shifted values, I never considered that they were a value in a bitfield. I'll try that out tonight. On further investigation, this really makes sense. Looking at ati.amd.com, the 9500 isn't even listed in discontinued products - like they want to pretend it never existed. The 9600, with the rv350 chipset, has half the pipes of a real r300 chip, and the rv350 tile count value is 0. I hadn't even considered that. Thanks for the help, and for the doc links. This will be good nightstand reading for a while. |
From: Roland S. <sr...@tu...> - 2008-03-17 15:54:25
|
Reid Linnemann wrote: > Written by Alex Deucher on 03/17/08 08:18>> >> On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: >>> Written by Alex Deucher on 03/16/08 19:55>> >>> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: >>> >> Jerome Glisse wrote: >>> >> > On Sat, 15 Mar 2008 11:00:25 -0500 >>> >> > Reid Linnemann <lr...@cs...> wrote: >>> >> > >>> >> >> Hi list, this is my first time posting and I'm not subscribed. >>> >> >> >>> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >>> >> >> >>> >> >> Some time ago I noticed that seemingly random pixels were not being >>> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. >>> >> >> But after a while it started to irk me, and then I remembered something >>> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >>> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >>> >> >> as a 9500. At one time this card was on a Windows box, and I tried >>> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard >>> >> >> pattern that indicated this. >>> >> >> >>> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >>> >> >> together in a multilayer image in gimp, alternating multiply/divide, and >>> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >>> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my >>> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all >>> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >>> >> >> any thoughts on this? >>> >> >> >>> >> >> I've attached the images with and without the overlaid grid for reference. >>> >> >> >>> >> >> >>> >> > >>> >> >>From memory code which detect card model and decide how many >>> >> > pipe to enable is wrong for many card. We were just optimistic. >>> >> > >>> >> > Cheers, >>> >> > Jerome Glisse <gl...@fr...> >>> >> >>> >> I'd be fine if I knew what code initialized the pipelines, then I might >>> >> be able to alter it to my needs. >>> >> >>> > >>> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c >>> > >>> > Alex >>> >>> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to >>> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just >>> appear as flickering holes in the gl context in the same checkerboard >>> pattern. Does that mean anything to you? >> The only valid values for pipe count (bits 3:1) for r3xx chips are 0 >> (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The >> documentation for these chips are available here: >> http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf >> http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf >> >> In your case I suspect you want 0. >> >> Alex > > > Ah, I see. I wondered why the tile pipe count constants were specified > as left-shifted values, I never considered that they were a value in a > bitfield. I'll try that out tonight. > > On further investigation, this really makes sense. Looking at > ati.amd.com, the 9500 isn't even listed in discontinued products - like > they want to pretend it never existed. The 9600, with the rv350 chipset, > has half the pipes of a real r300 chip, and the rv350 tile count value > is 0. I hadn't even considered that. > > Thanks for the help, and for the doc links. This will be good nightstand > reading for a while. If I remember correctly, there was another issue with the r300 chip (and the docs might not tell), it couldn't use hierarchical-z if only 1 pipe was activated due to the way this was coupled to the different pipes. Doesn't look like it gets enabled with the current driver however, so shouldn't be a problem. Roland |
From: Reid L. <lr...@cs...> - 2008-03-18 13:02:39
|
Written by Alex Deucher on 03/17/08 08:18>> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: >> Written by Alex Deucher on 03/16/08 19:55>> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: >> >> Jerome Glisse wrote: >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 >> >> > Reid Linnemann <lr...@cs...> wrote: >> >> > >> >> >> Hi list, this is my first time posting and I'm not subscribed. >> >> >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >> >> >> >> >> >> Some time ago I noticed that seemingly random pixels were not being >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. >> >> >> But after a while it started to irk me, and then I remembered something >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >> >> >> as a 9500. At one time this card was on a Windows box, and I tried >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard >> >> >> pattern that indicated this. >> >> >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >> >> >> any thoughts on this? >> >> >> >> >> >> I've attached the images with and without the overlaid grid for reference. >> >> >> >> >> >> >> >> > >> >> >>From memory code which detect card model and decide how many >> >> > pipe to enable is wrong for many card. We were just optimistic. >> >> > >> >> > Cheers, >> >> > Jerome Glisse <gl...@fr...> >> >> >> >> I'd be fine if I knew what code initialized the pipelines, then I might >> >> be able to alter it to my needs. >> >> >> > >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c >> > >> > Alex >> >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just >> appear as flickering holes in the gl context in the same checkerboard >> pattern. Does that mean anything to you? > > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > documentation for these chips are available here: > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > > In your case I suspect you want 0. > > Alex That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h fixed the tiling issue. Huzzah! |
From: Alex D. <ale...@gm...> - 2008-03-18 13:39:54
|
On Tue, Mar 18, 2008 at 9:02 AM, Reid Linnemann <lr...@cs...> wrote: > Written by Alex Deucher on 03/17/08 08:18>> > > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: > >> Written by Alex Deucher on 03/16/08 19:55>> > >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: > >> >> Jerome Glisse wrote: > >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 > >> >> > Reid Linnemann <lr...@cs...> wrote: > >> >> > > >> >> >> Hi list, this is my first time posting and I'm not subscribed. > >> >> >> > >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > >> >> >> > >> >> >> Some time ago I noticed that seemingly random pixels were not being > >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. > >> >> >> But after a while it started to irk me, and then I remembered something > >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but > >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > >> >> >> as a 9500. At one time this card was on a Windows box, and I tried > >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard > >> >> >> pattern that indicated this. > >> >> >> > >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them > >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and > >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the > >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my > >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all > >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > >> >> >> any thoughts on this? > >> >> >> > >> >> >> I've attached the images with and without the overlaid grid for reference. > >> >> >> > >> >> >> > >> >> > > >> >> >>From memory code which detect card model and decide how many > >> >> > pipe to enable is wrong for many card. We were just optimistic. > >> >> > > >> >> > Cheers, > >> >> > Jerome Glisse <gl...@fr...> > >> >> > >> >> I'd be fine if I knew what code initialized the pipelines, then I might > >> >> be able to alter it to my needs. > >> >> > >> > > >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > >> > > >> > Alex > >> > >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to > >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just > >> appear as flickering holes in the gl context in the same checkerboard > >> pattern. Does that mean anything to you? > > > > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 > > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > > documentation for these chips are available here: > > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > > > > In your case I suspect you want 0. > > > > Alex > > That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h > fixed the tiling issue. Huzzah! > Hey, send me your pci ids so I can push the fix upstream. Alex |
From: Reid L. <lr...@cs...> - 2008-03-18 13:46:08
|
Written by Alex Deucher on 03/18/08 08:39>> > On Tue, Mar 18, 2008 at 9:02 AM, Reid Linnemann <lr...@cs...> wrote: >> Written by Alex Deucher on 03/17/08 08:18>> >> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: >> >> Written by Alex Deucher on 03/16/08 19:55>> >> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: >> >> >> Jerome Glisse wrote: >> >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 >> >> >> > Reid Linnemann <lr...@cs...> wrote: >> >> >> > >> >> >> >> Hi list, this is my first time posting and I'm not subscribed. >> >> >> >> >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. >> >> >> >> >> >> >> >> Some time ago I noticed that seemingly random pixels were not being >> >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. >> >> >> >> But after a while it started to irk me, and then I remembered something >> >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but >> >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged >> >> >> >> as a 9500. At one time this card was on a Windows box, and I tried >> >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard >> >> >> >> pattern that indicated this. >> >> >> >> >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them >> >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and >> >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the >> >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my >> >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all >> >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have >> >> >> >> any thoughts on this? >> >> >> >> >> >> >> >> I've attached the images with and without the overlaid grid for reference. >> >> >> >> >> >> >> >> >> >> >> > >> >> >> >>From memory code which detect card model and decide how many >> >> >> > pipe to enable is wrong for many card. We were just optimistic. >> >> >> > >> >> >> > Cheers, >> >> >> > Jerome Glisse <gl...@fr...> >> >> >> >> >> >> I'd be fine if I knew what code initialized the pipelines, then I might >> >> >> be able to alter it to my needs. >> >> >> >> >> > >> >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c >> >> > >> >> > Alex >> >> >> >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to >> >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just >> >> appear as flickering holes in the gl context in the same checkerboard >> >> pattern. Does that mean anything to you? >> > >> > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 >> > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The >> > documentation for these chips are available here: >> > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf >> > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf >> > >> > In your case I suspect you want 0. >> > >> > Alex >> >> That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h >> fixed the tiling issue. Huzzah! >> > > Hey, send me your pci ids so I can push the fix upstream. > > Alex pciconf -lv output: vgapci0@pci0:1:0:0: class=0x030000 card=0x00021002 chip=0x41441002 rev=0x00 hdr=0x00 vendor = 'ATI Technologies Inc' device = 'Radeon 9500 Series (R300)' class = display subclass = VGA vgapci1@pci0:1:0:1: class=0x038000 card=0x00031002 chip=0x41641002 rev=0x00 hdr=0x00 vendor = 'ATI Technologies Inc' device = 'Radeon 9500 Series, secondary R300 (128bit mem bus)' class = display |
From: Alex D. <ale...@gm...> - 2008-03-19 22:10:45
|
On Tue, Mar 18, 2008 at 9:45 AM, Reid Linnemann <lr...@cs...> wrote: > Written by Alex Deucher on 03/18/08 08:39>> > > > > On Tue, Mar 18, 2008 at 9:02 AM, Reid Linnemann <lr...@cs...> wrote: > >> Written by Alex Deucher on 03/17/08 08:18>> > >> > On Mon, Mar 17, 2008 at 9:08 AM, Reid Linnemann <lr...@cs...> wrote: > >> >> Written by Alex Deucher on 03/16/08 19:55>> > >> >> > On Sun, Mar 16, 2008 at 8:49 PM, Reid Linnemann <lr...@cs...> wrote: > >> >> >> Jerome Glisse wrote: > >> >> >> > On Sat, 15 Mar 2008 11:00:25 -0500 > >> >> >> > Reid Linnemann <lr...@cs...> wrote: > >> >> >> > > >> >> >> >> Hi list, this is my first time posting and I'm not subscribed. > >> >> >> >> > >> >> >> >> I'm running Xorg 7.3 with dri on FreeBSD 7-STABLE. > >> >> >> >> > >> >> >> >> Some time ago I noticed that seemingly random pixels were not being > >> >> >> >> rendered in all GL contexts, and simply chalked it up to my card aging. > >> >> >> >> But after a while it started to irk me, and then I remembered something > >> >> >> >> about my sapphire 9500 - it's got one of the chips with 8 pipelines but > >> >> >> >> only 4 enabled, presumably a 9700 that didn't pass QA and was rebadged > >> >> >> >> as a 9500. At one time this card was on a Windows box, and I tried > >> >> >> >> enabling all 8 pipelines with the softmod, and got the checkerboard > >> >> >> >> pattern that indicated this. > >> >> >> >> > >> >> >> >> With this in mind, I took 10 dumps of a glxgears window and merged them > >> >> >> >> together in a multilayer image in gimp, alternating multiply/divide, and > >> >> >> >> overlaid a 16x16 grid. The artifacting lined up perfectly in the > >> >> >> >> checkerboard pattern. I'm now pretty convinced that somehow either my > >> >> >> >> system's DRM module, DRI, or radeon driver are erroneously enabling all > >> >> >> >> 8 pipelines on the card, resulting in mooky-stink rendering. Anyone have > >> >> >> >> any thoughts on this? > >> >> >> >> > >> >> >> >> I've attached the images with and without the overlaid grid for reference. > >> >> >> >> > >> >> >> >> > >> >> >> > > >> >> >> >>From memory code which detect card model and decide how many > >> >> >> > pipe to enable is wrong for many card. We were just optimistic. > >> >> >> > > >> >> >> > Cheers, > >> >> >> > Jerome Glisse <gl...@fr...> > >> >> >> > >> >> >> I'd be fine if I knew what code initialized the pipelines, then I might > >> >> >> be able to alter it to my needs. > >> >> >> > >> >> > > >> >> > search for R300_GB_TILE_PIPE_COUNT in r300_state.c > >> >> > > >> >> > Alex > >> >> > >> >> FWIW I've tried changing the value of this constant from 3<<1 (or 6) to > >> >> 2<<1 (or 4), but the bad tiles persist - only unrendered to. They just > >> >> appear as flickering holes in the gl context in the same checkerboard > >> >> pattern. Does that mean anything to you? > >> > > >> > The only valid values for pipe count (bits 3:1) for r3xx chips are 0 > >> > (RV3xx chips - 1 pipe) and 3 (R3xx chips - 2 pipes). The > >> > documentation for these chips are available here: > >> > http://ati.amd.com/developer/open_gpu_documentation/R3xx_3D_Registers.pdf > >> > http://ati.amd.com/developer/open_gpu_documentation/R5xx_Acceleration_v1.2.pdf > >> > > >> > In your case I suspect you want 0. > >> > > >> > Alex > >> > >> That was the ticket. Defining R300_GB_TILE_COUNT as 0 in r300_reg.h > >> fixed the tiling issue. Huzzah! > >> > > > > Hey, send me your pci ids so I can push the fix upstream. > > > > Alex > > pciconf -lv output: fix pushed to mesa: 65c4ced1ccea7ff88123296b7f0587faa6f23eef Thanks! Alex > > vgapci0@pci0:1:0:0: class=0x030000 card=0x00021002 chip=0x41441002 > rev=0x00 hdr=0x00 > vendor = 'ATI Technologies Inc' > device = 'Radeon 9500 Series (R300)' > class = display > subclass = VGA > vgapci1@pci0:1:0:1: class=0x038000 card=0x00031002 chip=0x41641002 > rev=0x00 hdr=0x00 > vendor = 'ATI Technologies Inc' > device = 'Radeon 9500 Series, secondary R300 (128bit mem bus)' > class = display > |