From: <ai...@ke...> - 2008-10-16 01:01:03
|
linux-core/drm_bo.c | 14 ++++-- linux-core/drm_objects.h | 6 ++ linux-core/radeon_buffer.c | 33 ++++++++------ linux-core/radeon_drv.c | 5 ++ linux-core/radeon_fb.c | 2 linux-core/radeon_gem.c | 7 ++- linux-core/radeon_pm.c | 31 +++++++++---- shared-core/r300_cmdbuf.c | 64 ++++++++++++++++++++++++++++ shared-core/radeon_cp.c | 102 ++++++++++++++++++++++++++++++++++++++++++++- shared-core/radeon_cs.c | 5 ++ shared-core/radeon_drv.h | 3 - 11 files changed, 240 insertions(+), 32 deletions(-) New commits: commit 26076bf24a4e720e389d0a3ea616a8350397fdfc Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:59:31 2008 +1000 radeon: add initial agp support. This add agpmode command line option. diff --git a/linux-core/radeon_drv.c b/linux-core/radeon_drv.c index 79bcc3e..f1fe301 100644 --- a/linux-core/radeon_drv.c +++ b/linux-core/radeon_drv.c @@ -39,6 +39,7 @@ int radeon_no_wb; int radeon_dynclks = 1; int radeon_r4xx_atom = 0; +int radeon_agpmode = 0; MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers\n"); module_param_named(no_wb, radeon_no_wb, int, 0444); @@ -52,6 +53,10 @@ module_param_named(dynclks, radeon_dynclks, int, 0444); MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); +MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); +module_param_named(agpmode, radeon_agpmode, int, 0444); + + static int dri_library_name(struct drm_device * dev, char * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 9825d70..190b143 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -2334,7 +2334,6 @@ int radeon_modeset_cp_suspend(struct drm_device *dev) int radeon_modeset_cp_resume(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - uint32_t tmp; radeon_do_wait_for_idle(dev_priv); #if __OS_HAS_AGP @@ -2358,6 +2357,95 @@ int radeon_modeset_cp_resume(struct drm_device *dev) return 0; } +#if __OS_HAS_AGP +int radeon_modeset_agp_init(struct drm_device *dev) +{ + drm_radeon_private_t *dev_priv = dev->dev_private; + struct drm_agp_mode mode; + struct drm_agp_info info; + int ret; + int default_mode; + uint32_t agp_status; + bool is_v3; + + /* Acquire AGP. */ + ret = drm_agp_acquire(dev); + if (ret) { + DRM_ERROR("Unable to acquire AGP: %d\n", ret); + return ret; + } + + ret = drm_agp_info(dev, &info); + if (ret) { + DRM_ERROR("Unable to get AGP info: %d\n", ret); + return ret; + } + + mode.mode = info.mode; + + agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; + is_v3 = !!(agp_status & RADEON_AGPv3_MODE); + + if (is_v3) { + default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; + } else { + if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4; + else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2; + else default_mode = 1; + } + + if (radeon_agpmode > 0) { + if ((radeon_agpmode < (is_v3 ? 4 : 1)) || + (radeon_agpmode > (is_v3 ? 8 : 4)) || + (radeon_agpmode & (radeon_agpmode - 1))) { + DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n", + radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4", + default_mode); + radeon_agpmode = default_mode; + } + else + DRM_INFO("AGP mode requested: %d\n", radeon_agpmode); + } else + radeon_agpmode = default_mode; + + mode.mode &= ~RADEON_AGP_MODE_MASK; + if (is_v3) { + switch(radeon_agpmode) { + case 8: + mode.mode |= RADEON_AGPv3_8X_MODE; + break; + case 4: + default: + mode.mode |= RADEON_AGPv3_4X_MODE; + break; + } + } else { + switch(radeon_agpmode) { + case 4: mode.mode |= RADEON_AGP_4X_MODE; + case 2: mode.mode |= RADEON_AGP_2X_MODE; + case 1: + default: + mode.mode |= RADEON_AGP_1X_MODE; + break; + } + } + + mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */ + + ret = drm_agp_enable(dev, mode); + if (ret) { + DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode); + return ret; + } + + /* workaround some hw issues */ + if (dev_priv->chip_family <= CHIP_R200) { + RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000); + } + return 0; +} +#endif + int radeon_modeset_cp_init(struct drm_device *dev) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2389,6 +2477,11 @@ int radeon_modeset_cp_init(struct drm_device *dev) dev_priv->new_memmap = true; r300_init_reg_flags(dev); + +#if __OS_HAS_AGP + if (dev_priv->flags & RADEON_IS_AGP) + radeon_modeset_agp_init(dev); +#endif return radeon_modeset_cp_resume(dev); } @@ -2478,6 +2571,7 @@ int radeon_static_clocks_init(struct drm_device *dev) } } radeon_force_some_clocks(dev); + return 0; } int radeon_driver_load(struct drm_device *dev, unsigned long flags) @@ -2523,6 +2617,12 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) DRM_DEBUG("%s card detected\n", ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); + if ((dev_priv->flags & RADEON_IS_AGP) && (radeon_agpmode == -1)) { + DRM_INFO("Forcing AGP to PCI mode\n"); + dev_priv->flags &= ~RADEON_IS_AGP; + } + + ret = drm_addmap(dev, drm_get_resource_start(dev, 2), drm_get_resource_len(dev, 2), _DRM_REGISTERS, _DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio); diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index c37f23d..a6ce129 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -459,6 +459,7 @@ extern int radeon_dynclks; extern int radeon_r4xx_atom; extern struct drm_ioctl_desc radeon_ioctls[]; extern int radeon_max_ioctl; +extern int radeon_agpmode; /* Check whether the given hardware address is inside the framebuffer or the * GART area. commit 8d9a11c55cf3692bd537c68044b4378aba53f438 Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:57:31 2008 +1000 radeon: add CS support for r100/r200 in 2D driver diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c index 725829b..b15e892 100644 --- a/shared-core/r300_cmdbuf.c +++ b/shared-core/r300_cmdbuf.c @@ -35,6 +35,7 @@ #include "drm.h" #include "radeon_drm.h" #include "radeon_drv.h" +#include "radeon_reg.h" #include "r300_reg.h" #define R300_SIMULTANEOUS_CLIPRECTS 4 @@ -309,6 +310,69 @@ void r300_init_reg_flags(struct drm_device *dev) ADD_RANGE(RADEON_RE_WIDTH_HEIGHT, 1); ADD_RANGE(RADEON_AUX_SC_CNTL, 1); ADD_RANGE(RADEON_RB3D_DSTCACHE_CTLSTAT, 1); + ADD_RANGE(RADEON_RB3D_PLANEMASK, 1); + ADD_RANGE(RADEON_SE_CNTL, 1); + ADD_RANGE(RADEON_PP_CNTL, 1); + ADD_RANGE(RADEON_RB3D_CNTL, 1); + ADD_RANGE_MARK(RADEON_RB3D_COLOROFFSET, 1, MARK_CHECK_OFFSET); + ADD_RANGE(RADEON_RB3D_COLORPITCH, 1); + ADD_RANGE(RADEON_RB3D_BLENDCNTL, 1); + + if (dev_priv->chip_family >= CHIP_R200) { + ADD_RANGE(R200_PP_CNTL_X, 1); + ADD_RANGE(R200_PP_TXMULTI_CTL_0, 1); + ADD_RANGE(R200_SE_VTX_STATE_CNTL, 1); + ADD_RANGE(R200_RE_CNTL, 1); + ADD_RANGE(R200_SE_VTE_CNTL, 1); + ADD_RANGE(R200_SE_VAP_CNTL, 1); + + ADD_RANGE(R200_PP_TXFILTER_0, 1); + ADD_RANGE(R200_PP_TXFORMAT_0, 1); + ADD_RANGE(R200_PP_TXFORMAT_X_0, 1); + ADD_RANGE(R200_PP_TXSIZE_0, 1); + ADD_RANGE(R200_PP_TXPITCH_0, 1); + ADD_RANGE(R200_PP_TFACTOR_0, 1); + + ADD_RANGE(R200_PP_TXFILTER_1, 1); + ADD_RANGE(R200_PP_TXFORMAT_1, 1); + ADD_RANGE(R200_PP_TXFORMAT_X_1, 1); + ADD_RANGE(R200_PP_TXSIZE_1, 1); + ADD_RANGE(R200_PP_TXPITCH_1, 1); + ADD_RANGE(R200_PP_TFACTOR_1, 1); + + ADD_RANGE_MARK(R200_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(R200_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(R200_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(R200_PP_TXOFFSET_3, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(R200_PP_TXOFFSET_4, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(R200_PP_TXOFFSET_5, 1, MARK_CHECK_OFFSET); + + ADD_RANGE(R200_SE_VTX_FMT_0, 1); + ADD_RANGE(R200_SE_VTX_FMT_1, 1); + ADD_RANGE(R200_PP_TXCBLEND_0, 1); + ADD_RANGE(R200_PP_TXCBLEND2_0, 1); + ADD_RANGE(R200_PP_TXABLEND_0, 1); + ADD_RANGE(R200_PP_TXABLEND2_0, 1); + + } else { + + ADD_RANGE(RADEON_PP_TXFILTER_0, 1); + ADD_RANGE(RADEON_PP_TXFORMAT_0, 1); + ADD_RANGE(RADEON_PP_TEX_SIZE_0, 1); + ADD_RANGE(RADEON_PP_TEX_PITCH_0, 1); + + ADD_RANGE(RADEON_PP_TXFILTER_1, 1); + ADD_RANGE(RADEON_PP_TXFORMAT_1, 1); + ADD_RANGE(RADEON_PP_TEX_SIZE_1, 1); + ADD_RANGE(RADEON_PP_TEX_PITCH_1, 1); + + ADD_RANGE(RADEON_PP_TXCBLEND_0, 1); + ADD_RANGE(RADEON_PP_TXABLEND_0, 1); + ADD_RANGE(RADEON_SE_VTX_FMT, 1); + ADD_RANGE_MARK(RADEON_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(RADEON_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET); + ADD_RANGE_MARK(RADEON_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET); + } } } diff --git a/shared-core/radeon_cs.c b/shared-core/radeon_cs.c index a00ec21..f914713 100644 --- a/shared-core/radeon_cs.c +++ b/shared-core/radeon_cs.c @@ -139,10 +139,15 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_device *dev, struct offset >>= 10; val |= offset; break; + case RADEON_RB3D_COLOROFFSET: case R300_RB3D_COLOROFFSET0: case R300_ZB_DEPTHOFFSET: case R300_TX_OFFSET_0: case R300_TX_OFFSET_0+4: + case R200_PP_TXOFFSET_0: + case R200_PP_TXOFFSET_1: + case RADEON_PP_TXOFFSET_0: + case RADEON_PP_TXOFFSET_1: ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset); if (ret) return ret; commit 66740cbd5411a870dc6cc282c19a72809dd992be Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:55:24 2008 +1000 radeon: fixup interrupt suspend/resume diff --git a/linux-core/radeon_pm.c b/linux-core/radeon_pm.c index 0a068cb..6b1e6f8 100644 --- a/linux-core/radeon_pm.c +++ b/linux-core/radeon_pm.c @@ -69,6 +69,11 @@ int radeon_suspend(struct drm_device *dev, pm_message_t state) radeon_modeset_cp_suspend(dev); + /* Disable *all* interrupts */ + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) + RADEON_WRITE(R500_DxMODE_INT_MASK, 0); + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); + if (dev_priv->flags & RADEON_IS_PCIE) { memcpy_fromio(dev_priv->mm.pcie_table_backup, dev_priv->mm.pcie_table.kmap.virtual, RADEON_PCIGART_TABLE_SIZE); } @@ -155,7 +160,9 @@ int radeon_resume(struct drm_device *dev) /* reset swi reg */ RADEON_WRITE(RADEON_LAST_SWI_REG, dev_priv->counter); -// radeon_enable_interrupt(dev); + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) + RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); + RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); /* reset the context for userspace */ if (dev->primary->master) { commit 318770a78dc563a9a2780614fa3bf6c813584889 Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:53:55 2008 +1000 radeon: fixup suspend/resume bus master enable diff --git a/linux-core/radeon_pm.c b/linux-core/radeon_pm.c index 1a814d9..0a068cb 100644 --- a/linux-core/radeon_pm.c +++ b/linux-core/radeon_pm.c @@ -97,12 +97,14 @@ int radeon_resume(struct drm_device *dev) pci_restore_state(dev->pdev); if (pci_enable_device(dev->pdev)) return -1; - pci_set_master(dev->pdev); - /* Turn on bus mastering */ - tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE(RADEON_BUS_CNTL, tmp); + /* Turn on bus mastering -todo fix properly */ + if (dev_priv->chip_family < CHIP_RV380) { + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE(RADEON_BUS_CNTL, tmp); + } + DRM_ERROR("\n"); /* on atom cards re init the whole card and set the modes again */ @@ -113,6 +115,8 @@ int radeon_resume(struct drm_device *dev) radeon_combios_asic_init(dev); } + pci_set_master(dev->pdev); + for (i = 0; i < 8; i++) RADEON_WRITE(RADEON_BIOS_0_SCRATCH + (i * 4), dev_priv->pmregs.bios_scratch[i]); @@ -160,7 +164,7 @@ int radeon_resume(struct drm_device *dev) master_priv->sarea_priv->ctx_owner = 0; } - /* unpin the front buffers */ + /* pin the front buffers */ list_for_each_entry(fb, &dev->mode_config.fb_kernel_list, filp_head) { struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); commit 9c5819fc60808b00949f6aee55424f17a8b4f419 Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:53:26 2008 +1000 radeon: re-enable hw blits for copying from VRAM diff --git a/linux-core/radeon_buffer.c b/linux-core/radeon_buffer.c index 9090000..e5a9089 100644 --- a/linux-core/radeon_buffer.c +++ b/linux-core/radeon_buffer.c @@ -411,9 +411,6 @@ int radeon_move(struct drm_buffer_object * bo, return 0; } - /* disable these blit moves for now that appear to be failing */ - goto fallback; - if (new_mem->mem_type == DRM_BO_MEM_VRAM) { if (radeon_move_vram(bo, evict, no_wait, new_mem)) goto fallback; commit b18e6b0a0d9ef6902e4be1809ba710200f4c37be Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:52:53 2008 +1000 radeon: fix buffer copying for VRAM->TT diff --git a/linux-core/radeon_buffer.c b/linux-core/radeon_buffer.c index c375100..9090000 100644 --- a/linux-core/radeon_buffer.c +++ b/linux-core/radeon_buffer.c @@ -306,22 +306,32 @@ static int radeon_move_flip(struct drm_buffer_object * bo, int ret; tmp_mem = *new_mem; - tmp_mem.mm_node = NULL; - tmp_mem.proposed_flags = DRM_BO_FLAG_MEM_TT; - ret = drm_bo_mem_space(bo, &tmp_mem, no_wait); - if (ret) - return ret; + /* if we are flipping into LOCAL memory we have no TTM so create one */ + if (new_mem->mem_type == DRM_BO_MEM_LOCAL) { + tmp_mem.mm_node = NULL; + tmp_mem.proposed_flags = DRM_BO_FLAG_MEM_TT; - ret = drm_ttm_bind(bo->ttm, &tmp_mem); - if (ret) - goto out_cleanup; + ret = drm_bo_mem_space(bo, &tmp_mem, no_wait); + if (ret) + return ret; + + ret = drm_ttm_bind(bo->ttm, &tmp_mem); + if (ret) + goto out_cleanup; + } ret = radeon_move_blit(bo, 1, no_wait, &tmp_mem, &bo->mem); if (ret) goto out_cleanup; - ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem); + if (new_mem->mem_type == DRM_BO_MEM_LOCAL) { + ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem); + } else { + tmp_mem.mm_node = NULL; + new_mem->mm_node = NULL; + } + out_cleanup: if (tmp_mem.mm_node) { mutex_lock(&dev->struct_mutex); commit 3e3280eccc38cd080cbab7b471aad1b9cd12fd1b Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:52:28 2008 +1000 radeon: move memcpy until after CP is stopped diff --git a/linux-core/radeon_pm.c b/linux-core/radeon_pm.c index de10779..1a814d9 100644 --- a/linux-core/radeon_pm.c +++ b/linux-core/radeon_pm.c @@ -63,16 +63,16 @@ int radeon_suspend(struct drm_device *dev, pm_message_t state) if (!(dev_priv->flags & RADEON_IS_IGP)) drm_bo_evict_mm(dev, DRM_BO_MEM_VRAM, 0); - if (dev_priv->flags & RADEON_IS_PCIE) { - memcpy_fromio(dev_priv->mm.pcie_table_backup, dev_priv->mm.pcie_table.kmap.virtual, RADEON_PCIGART_TABLE_SIZE); - } - dev_priv->pmregs.crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL); for (i = 0; i < 8; i++) dev_priv->pmregs.bios_scratch[i] = RADEON_READ(RADEON_BIOS_0_SCRATCH + (i * 4)); radeon_modeset_cp_suspend(dev); + if (dev_priv->flags & RADEON_IS_PCIE) { + memcpy_fromio(dev_priv->mm.pcie_table_backup, dev_priv->mm.pcie_table.kmap.virtual, RADEON_PCIGART_TABLE_SIZE); + } + pci_save_state(dev->pdev); if (state.event == PM_EVENT_SUSPEND) { commit 09f99dc5febecac63d8c636abadea53e89d879aa Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:51:56 2008 +1000 drm: remove stray debug code diff --git a/linux-core/drm_bo.c b/linux-core/drm_bo.c index 93df229..36af51c 100644 --- a/linux-core/drm_bo.c +++ b/linux-core/drm_bo.c @@ -2099,7 +2099,6 @@ void drm_bo_evict_mm(struct drm_device *dev, int mem_type, int no_wait) int ret; /* evict all buffers on the LRU - won't evict pinned buffers */ - drm_mm_dump(&man->manager); mutex_lock(&dev->struct_mutex); do { lru = &man->lru; commit d958cd7bb95558aa6c49824e2ae2b302f1433d2e Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:51:31 2008 +1000 radeon: use discardable flags on no backing store objects diff --git a/linux-core/radeon_fb.c b/linux-core/radeon_fb.c index 8c9461d..8d4181e 100644 --- a/linux-core/radeon_fb.c +++ b/linux-core/radeon_fb.c @@ -728,7 +728,7 @@ int radeonfb_create(struct drm_device *dev, uint32_t fb_width, uint32_t fb_heigh size = mode_cmd.pitch * mode_cmd.height; aligned_size = ALIGN(size, PAGE_SIZE); - fbo = radeon_gem_object_alloc(dev, aligned_size, 1, RADEON_GEM_DOMAIN_VRAM); + fbo = radeon_gem_object_alloc(dev, aligned_size, 1, RADEON_GEM_DOMAIN_VRAM, 0); if (!fbo) { printk(KERN_ERR "failed to allocate framebuffer\n"); ret = -ENOMEM; diff --git a/linux-core/radeon_gem.c b/linux-core/radeon_gem.c index 225f026..5e2ad98 100644 --- a/linux-core/radeon_gem.c +++ b/linux-core/radeon_gem.c @@ -74,7 +74,7 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, } struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment, - int initial_domain) + int initial_domain, bool discardable) { struct drm_gem_object *obj; struct drm_radeon_gem_object *obj_priv; @@ -97,6 +97,9 @@ struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, flags |= DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE; + if (discardable) + flags |= DRM_BO_FLAG_DISCARDABLE; + if (alignment == 0) alignment = PAGE_SIZE; @@ -129,7 +132,7 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data, /* create a gem object to contain this object in */ args->size = roundup(args->size, PAGE_SIZE); - obj = radeon_gem_object_alloc(dev, args->size, args->alignment, args->initial_domain); + obj = radeon_gem_object_alloc(dev, args->size, args->alignment, args->initial_domain, args->no_backing_store); if (!obj) return -EINVAL; diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 3490ddb..c37f23d 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -1672,7 +1672,7 @@ int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data, int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment, - int initial_domain); + int initial_domain, bool discardable); int radeon_modeset_init(struct drm_device *dev); void radeon_modeset_cleanup(struct drm_device *dev); extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr); commit 11320fd6b106c1255f3fad0860cb4da71697b46a Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:50:31 2008 +1000 drm: add discardable flag. This discards memory contents on suspend/resume with the hope the upper layers know something we don't. diff --git a/linux-core/drm_bo.c b/linux-core/drm_bo.c index 94a8155..93df229 100644 --- a/linux-core/drm_bo.c +++ b/linux-core/drm_bo.c @@ -2098,22 +2098,29 @@ void drm_bo_evict_mm(struct drm_device *dev, int mem_type, int no_wait) struct list_head *lru; int ret; /* evict all buffers on the LRU - won't evict pinned buffers */ - + + drm_mm_dump(&man->manager); mutex_lock(&dev->struct_mutex); do { lru = &man->lru; - if (lru->next == lru) { +redo: + if (lru->next == &man->lru) { DRM_ERROR("lru empty\n"); break; } entry = list_entry(lru->next, struct drm_buffer_object, lru); + + if (entry->mem.flags & DRM_BO_FLAG_DISCARDABLE) { + lru = lru->next; + goto redo; + } + atomic_inc(&entry->usage); mutex_unlock(&dev->struct_mutex); mutex_lock(&entry->mutex); - DRM_ERROR("Evicting %p %d\n", entry, entry->num_pages); ret = drm_bo_evict(entry, mem_type, no_wait); mutex_unlock(&entry->mutex); diff --git a/linux-core/drm_objects.h b/linux-core/drm_objects.h index acb10f9..0c8ffe9 100644 --- a/linux-core/drm_objects.h +++ b/linux-core/drm_objects.h @@ -117,6 +117,12 @@ struct drm_fence_arg { */ #define DRM_BO_FLAG_NO_MOVE (1ULL << 8) +/* + * Mask: if set the note the buffer contents are discardable + * Flags: if set the buffer contents are discardable on migration + */ +#define DRM_BO_FLAG_DISCARDABLE (1ULL << 9) + /* Mask: Make sure the buffer is in cached memory when mapped. In conjunction * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART * with unsnooped PTEs instead of snooped, by using chipset-specific cache commit fc33686ef044a4a59d48da2a648a0c2d0a1a7fd6 Author: Dave Airlie <ai...@re...> Date: Thu Oct 16 10:49:58 2008 +1000 drm/radeon: initial suspend/resume fix. This enables the evict code and also sets radeon up to allow evict from VRAM to LOCAL diff --git a/linux-core/drm_bo.c b/linux-core/drm_bo.c index ecf65c2..94a8155 100644 --- a/linux-core/drm_bo.c +++ b/linux-core/drm_bo.c @@ -2126,7 +2126,7 @@ void drm_bo_evict_mm(struct drm_device *dev, int mem_type, int no_wait) drm_bo_usage_deref_unlocked(&entry); mutex_lock(&dev->struct_mutex); - } while(0); + } while(1); mutex_unlock(&dev->struct_mutex); diff --git a/linux-core/radeon_buffer.c b/linux-core/radeon_buffer.c index fe2aa6f..c375100 100644 --- a/linux-core/radeon_buffer.c +++ b/linux-core/radeon_buffer.c @@ -436,6 +436,6 @@ uint64_t radeon_evict_flags(struct drm_buffer_object *bo) case DRM_BO_MEM_TT: return DRM_BO_FLAG_MEM_LOCAL; default: - return DRM_BO_FLAG_MEM_TT; + return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_MEM_LOCAL; } } |
From: <ai...@ke...> - 2008-11-10 05:41:36
|
linux-core/Makefile.kernel | 2 linux-core/ObjectID.h | 36 + linux-core/atombios.h | 803 +++++++++++++++++++++++++++++++++-------- linux-core/drm_bo.c | 3 linux-core/drm_crtc.c | 2 linux-core/drm_crtc_helper.c | 29 + linux-core/drm_crtc_helper.h | 2 linux-core/drm_objects.h | 13 linux-core/drm_ttm.c | 29 + linux-core/drm_uncached.c | 138 +++++++ linux-core/radeon_connectors.c | 19 linux-core/radeon_cursor.c | 4 linux-core/radeon_fb.c | 5 linux-core/radeon_fence.c | 13 linux-core/radeon_gem.c | 13 shared-core/radeon_cp.c | 42 +- shared-core/radeon_drv.h | 27 - 17 files changed, 1005 insertions(+), 175 deletions(-) New commits: commit 15464f5181538d01e8fc016211daa1a824b89531 Author: Dave Airlie <ai...@re...> Date: Mon Nov 10 15:38:32 2008 +1000 radeon: add gart useable size to report to userspace diff --git a/linux-core/radeon_gem.c b/linux-core/radeon_gem.c index f338e64..2ed9bfc 100644 --- a/linux-core/radeon_gem.c +++ b/linux-core/radeon_gem.c @@ -68,7 +68,7 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, args->vram_visible = dev_priv->mm.vram_visible; args->gart_start = dev_priv->mm.gart_start; - args->gart_size = dev_priv->mm.gart_size; + args->gart_size = dev_priv->mm.gart_useable; return 0; } @@ -680,6 +680,8 @@ int radeon_alloc_gart_objects(struct drm_device *dev) dev_priv->mm.ring.bo, dev_priv->mm.ring.bo->offset, dev_priv->mm.ring.kmap.virtual, dev_priv->mm.ring_read.bo, dev_priv->mm.ring_read.bo->offset, dev_priv->mm.ring_read.kmap.virtual); + dev_priv->mm.gart_useable -= RADEON_DEFAULT_RING_SIZE + PAGE_SIZE; + /* init the indirect buffers */ radeon_gem_ib_init(dev); radeon_gem_dma_bufs_init(dev); @@ -989,6 +991,7 @@ int radeon_gem_mm_init(struct drm_device *dev) dev_priv->mm.gart_size = (32 * 1024 * 1024); dev_priv->mm.gart_start = 0; + dev_priv->mm.gart_useable = dev_priv->mm.gart_size; ret = radeon_gart_init(dev); if (ret) return -EINVAL; @@ -1293,6 +1296,7 @@ static int radeon_gem_ib_init(struct drm_device *dev) goto free_all; } + dev_priv->mm.gart_useable -= RADEON_IB_SIZE * RADEON_NUM_IB; dev_priv->ib_alloc_bitmap = 0; dev_priv->cs.ib_get = radeon_gem_ib_get; @@ -1529,6 +1533,7 @@ static int radeon_gem_dma_bufs_init(struct drm_device *dev) DRM_ERROR("Failed to mmap DMA buffers\n"); return -ENOMEM; } + dev_priv->mm.gart_useable -= size; DRM_DEBUG("\n"); radeon_gem_addbufs(dev); diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index cd68379..cf3084e 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -274,6 +274,8 @@ struct radeon_mm_info { uint64_t gart_start; uint64_t gart_size; + uint64_t gart_useable; + void *pcie_table_backup; struct radeon_mm_obj pcie_table; commit 532c63cddd273bffab715e3d387268abe164f148 Author: Dave Airlie <ai...@re...> Date: Mon Nov 10 15:37:51 2008 +1000 radeon: upgrade atom headers diff --git a/linux-core/ObjectID.h b/linux-core/ObjectID.h index 4b106cf..f1f18a4 100644 --- a/linux-core/ObjectID.h +++ b/linux-core/ObjectID.h @@ -78,6 +78,10 @@ #define ENCODER_OBJECT_ID_DP_DP501 0x1D #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20 +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21 + +#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF /****************************************************/ /* Connector Object ID Definition */ @@ -118,6 +122,8 @@ #define GRAPH_OBJECT_ENUM_ID2 0x02 #define GRAPH_OBJECT_ENUM_ID3 0x03 #define GRAPH_OBJECT_ENUM_ID4 0x04 +#define GRAPH_OBJECT_ENUM_ID5 0x05 +#define GRAPH_OBJECT_ENUM_ID6 0x06 /****************************************************/ /* Graphics Object ID Bit definition */ @@ -173,7 +179,7 @@ #define ENCODER_SI178_ENUM_ID1 0x2117 #define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 #define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 -#define ENCODER_VT1625_ENUM_ID1 0x211A +#define ENCODER_VT1625_ENUM_ID1 0x211A #define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B #define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C #define ENCODER_DP_DP501_ENUM_ID1 0x211D @@ -323,6 +329,26 @@ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) +#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) + +#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) + /****************************************************/ /* Connector Object ID definition - Shared with BIOS */ /****************************************************/ @@ -453,6 +479,14 @@ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) +#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + /****************************************************/ /* Router Object ID definition - Shared with BIOS */ /****************************************************/ diff --git a/linux-core/atombios.h b/linux-core/atombios.h index 2e7dc6c..9932b09 100644 --- a/linux-core/atombios.h +++ b/linux-core/atombios.h @@ -266,7 +266,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT VRAM_BlockDetectionByStrap; + USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios USHORT MemoryCleanUp; //Atomic Table, only used by Bios USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components @@ -276,9 +276,9 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock - USHORT VRAM_GetCurrentInfoBlock; + USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT MemoryTraining; + USHORT MemoryTraining; //Atomic Table, used only by Bios USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 @@ -296,11 +296,12 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT DPEncoderService; //Function Table,only used by Bios }ATOM_MASTER_LIST_OF_COMMAND_TABLES; +// For backward compatible #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction - #define UNIPHYTransmitterControl DIG1TransmitterControl #define LVTMATransmitterControl DIG2TransmitterControl -#define SetCRTC_DPM_State GetConditionalGoldenSetting +#define SetCRTC_DPM_State GetConditionalGoldenSetting +#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange typedef struct _ATOM_MASTER_COMMAND_TABLE { @@ -308,6 +309,9 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; }ATOM_MASTER_COMMAND_TABLE; +/****************************************************************************/ +// Structures used in every command table +/****************************************************************************/ typedef struct _ATOM_TABLE_ATTRIBUTE { #if ATOM_BIG_ENDIAN @@ -327,23 +331,20 @@ typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS USHORT susAccess; }ATOM_TABLE_ATTRIBUTE_ACCESS; +/****************************************************************************/ // Common header for all command tables. -//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. -//And the pointer actually points to this header. - +// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +// And the pointer actually points to this header. +/****************************************************************************/ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { ATOM_COMMON_TABLE_HEADER CommonHeader; ATOM_TABLE_ATTRIBUTE TableAttribute; }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; - -typedef struct _ASIC_INIT_PARAMETERS -{ - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit -}ASIC_INIT_PARAMETERS; - +/****************************************************************************/ +// Structures used by ComputeMemoryEnginePLLTable +/****************************************************************************/ #define COMPUTE_MEMORY_PLL_PARAM 1 #define COMPUTE_ENGINE_PLL_PARAM 2 @@ -380,6 +381,57 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL +typedef struct _ATOM_COMPUTE_CLOCK_FREQ +{ +#if ATOM_BIG_ENDIAN + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM + ULONG ulClockFreq:24; // in unit of 10kHz +#else + ULONG ulClockFreq:24; // in unit of 10kHz + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM +#endif +}ATOM_COMPUTE_CLOCK_FREQ; + +typedef struct _ATOM_S_MPLL_FB_DIVIDER +{ + USHORT usFbDivFrac; + USHORT usFbDiv; +}ATOM_S_MPLL_FB_DIVIDER; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 +{ + union + { + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter + }; + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + UCHAR ucCntlFlag; //Output Parameter + UCHAR ucReserved; +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; + +// ucCntlFlag +#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 +#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 +#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 + +typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulReserved[2]; +}DYNAMICE_MEMORY_SETTINGS_PARAMETER; + +typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulMemoryClock; + ULONG ulReserved; +}DYNAMICE_ENGINE_SETTINGS_PARAMETER; + +/****************************************************************************/ +// Structures used by SetEngineClockTable +/****************************************************************************/ typedef struct _SET_ENGINE_CLOCK_PARAMETERS { ULONG ulTargetEngineClock; //In 10Khz unit @@ -391,7 +443,9 @@ typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_ENGINE_CLOCK_PS_ALLOCATION; - +/****************************************************************************/ +// Structures used by SetMemoryClockTable +/****************************************************************************/ typedef struct _SET_MEMORY_CLOCK_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -403,13 +457,24 @@ typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_MEMORY_CLOCK_PS_ALLOCATION; +/****************************************************************************/ +// Structures used by ASIC_Init.ctb +/****************************************************************************/ +typedef struct _ASIC_INIT_PARAMETERS +{ + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit +}ASIC_INIT_PARAMETERS; + typedef struct _ASIC_INIT_PS_ALLOCATION { ASIC_INIT_PARAMETERS sASICInitClocks; SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure }ASIC_INIT_PS_ALLOCATION; - +/****************************************************************************/ +// Structure used by DynamicClockGatingTable.ctb +/****************************************************************************/ typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE @@ -417,7 +482,9 @@ typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS }DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS - +/****************************************************************************/ +// Structure used by EnableASIC_StaticPwrMgtTable.ctb +/****************************************************************************/ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE @@ -425,7 +492,9 @@ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS - +/****************************************************************************/ +// Structures used by DAC_LoadDetectionTable.ctb +/****************************************************************************/ typedef struct _DAC_LOAD_DETECTION_PARAMETERS { USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} @@ -436,14 +505,15 @@ typedef struct _DAC_LOAD_DETECTION_PARAMETERS // DAC_LOAD_DETECTION_PARAMETERS.ucMisc #define DAC_LOAD_MISC_YPrPb 0x01 - typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION { DAC_LOAD_DETECTION_PARAMETERS sDacload; ULONG Reserved[2];// Don't set this one, allocation for EXT DAC }DAC_LOAD_DETECTION_PS_ALLOCATION; - +/****************************************************************************/ +// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb +/****************************************************************************/ typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -455,14 +525,11 @@ typedef struct _DAC_ENCODER_CONTROL_PARAMETERS #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS -typedef struct _TV_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder -}TV_ENCODER_CONTROL_PARAMETERS; - +/****************************************************************************/ +// Structures used by DIG1EncoderControlTable +// DIG2EncoderControlTable +// ExternalEncoderControlTable +/****************************************************************************/ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -487,7 +554,6 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS }DIG_ENCODER_CONTROL_PARAMETERS; #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS -#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION //ucConfig #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 @@ -518,6 +584,56 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS #define ATOM_ENCODER_MODE_CV 14 #define ATOM_ENCODER_MODE_CRT 15 +typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:2; + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucReserved:1; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz +#else + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + UCHAR ucReserved:1; + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucReserved1:2; +#endif +}ATOM_DIG_ENCODER_CONFIG_V2; + + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + ATOM_DIG_ENCODER_CONFIG_V2 acConfig; + UCHAR ucAction; + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucReserved[2]; +}DIG_ENCODER_CONTROL_PARAMETERS_V2; + +//ucConfig +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 + +/****************************************************************************/ +// Structures used by UNIPHYTransmitterControlTable +// LVTMATransmitterControlTable +// DVOOutputControlTable +/****************************************************************************/ typedef struct _ATOM_DP_VS_MODE { UCHAR ucLaneSel; @@ -595,7 +711,82 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS #define ATOM_TRANSMITTER_ACTION_SETUP 10 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 -/****************************Device Output Control Command Table Definitions**********************/ + +// Following are used for DigTransmitterControlTable ver1.2 +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucReserved:1; + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector +#else + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucReserved:1; + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V2; + +//ucConfig +//Bit0 +#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 + +//Bit1 +#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 + +//Bit2 +#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 + +// Bit3 +#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP +#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP + +// Bit4 +#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 + +// Bit7:6 +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; + + +/****************************************************************************/ +// Structures used by DAC1OuputControlTable +// DAC2OuputControlTable +// LVTMAOutputControlTable (Before DEC30) +// TMDSAOutputControlTable (Before DEC30) +/****************************************************************************/ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE @@ -634,7 +825,9 @@ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS -/**************************************************************************/ +/****************************************************************************/ +// Structures used by BlankCRTCTable +/****************************************************************************/ typedef struct _BLANK_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -645,7 +838,11 @@ typedef struct _BLANK_CRTC_PARAMETERS }BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS - +/****************************************************************************/ +// Structures used by EnableCRTCTable +// EnableCRTCMemReqTable +// UpdateCRTC_DoubleBufferRegistersTable +/****************************************************************************/ typedef struct _ENABLE_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -654,7 +851,9 @@ typedef struct _ENABLE_CRTC_PARAMETERS }ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS - +/****************************************************************************/ +// Structures used by SetCRTC_OverScanTable +/****************************************************************************/ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { USHORT usOverscanRight; // right @@ -666,7 +865,9 @@ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS }SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS - +/****************************************************************************/ +// Structures used by SetCRTC_ReplicationTable +/****************************************************************************/ typedef struct _SET_CRTC_REPLICATION_PARAMETERS { UCHAR ucH_Replication; // horizontal replication @@ -676,7 +877,9 @@ typedef struct _SET_CRTC_REPLICATION_PARAMETERS }SET_CRTC_REPLICATION_PARAMETERS; #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS - +/****************************************************************************/ +// Structures used by SelectCRTC_SourceTable +/****************************************************************************/ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -713,6 +916,10 @@ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 //#define ATOM_ENCODER_MODE_CV 14 //#define ATOM_ENCODER_MODE_CRT 15 +/****************************************************************************/ +// Structures used by SetPixelClockTable +// GetPixelClockTable +/****************************************************************************/ //Major revision=1., Minor revision=1 typedef struct _PIXEL_CLOCK_PARAMETERS { @@ -728,7 +935,6 @@ typedef struct _PIXEL_CLOCK_PARAMETERS UCHAR ucPadding; }PIXEL_CLOCK_PARAMETERS; - //Major revision=1., Minor revision=2, add ucMiscIfno //ucMiscInfo: #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 @@ -799,6 +1005,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST +/****************************************************************************/ +// Structures used by AdjustDisplayPllTable +/****************************************************************************/ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { USHORT usPixelClock; @@ -816,6 +1025,9 @@ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS +/****************************************************************************/ +// Structures used by EnableYUVTable +/****************************************************************************/ typedef struct _ENABLE_YUV_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) @@ -824,20 +1036,27 @@ typedef struct _ENABLE_YUV_PARAMETERS }ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS +/****************************************************************************/ +// Structures used by GetMemoryClockTable +/****************************************************************************/ typedef struct _GET_MEMORY_CLOCK_PARAMETERS { ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit } GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS - +/****************************************************************************/ +// Structures used by GetEngineClockTable +/****************************************************************************/ typedef struct _GET_ENGINE_CLOCK_PARAMETERS { ULONG ulReturnEngineClock; // current engine speed in 10KHz unit } GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS - +/****************************************************************************/ +// Following Structures and constant may be obsolete +/****************************************************************************/ //Maxium 8 bytes,the data read in will be placed in the parameter space. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS @@ -887,6 +1106,9 @@ typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS /**************************************************************************/ #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS +/****************************************************************************/ +// Structures used by PowerConnectorDetectionTable +/****************************************************************************/ typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected @@ -903,6 +1125,10 @@ typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; /****************************LVDS SS Command Table Definitions**********************/ + +/****************************************************************************/ +// Structures used by EnableSpreadSpectrumOnPPLLTable +/****************************************************************************/ typedef struct _ENABLE_LVDS_SS_PARAMETERS { USHORT usSpreadSpectrumPercentage; @@ -948,6 +1174,9 @@ typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ typedef struct _MEMORY_TRAINING_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -955,8 +1184,14 @@ typedef struct _MEMORY_TRAINING_PARAMETERS #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS - /****************************LVDS and other encoder command table definitions **********************/ + + +/****************************************************************************/ +// Structures used by LVDSEncoderControlTable (Before DCE30) +// LVTMAEncoderControlTable (Before DCE30) +// TMDSAEncoderControlTable (Before DCE30) +/****************************************************************************/ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -976,19 +1211,6 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS -{ - UCHAR ucEnable; // Enable or Disable External TMDS encoder - UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} - UCHAR ucPadding[2]; -}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION -{ - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; - //ucTableFormatRevision=1,ucTableContentRevision=2 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 @@ -1028,6 +1250,32 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 + +#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 + +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS +{ + UCHAR ucEnable; // Enable or Disable External TMDS encoder + UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} + UCHAR ucPadding[2]; +}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; + #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 @@ -1036,7 +1284,15 @@ typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; +typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION +{ + DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; +/****************************************************************************/ +// Structures used by DVOEncoderControlTable +/****************************************************************************/ //ucTableFormatRevision=1,ucTableContentRevision=3 //ucDVOConfig: @@ -1062,15 +1318,6 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 // bit1=0: non-coherent mode // =1: coherent mode -#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 - //========================================================================================== //Only change is here next time when changing encoder parameter definitions again! #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 @@ -1114,20 +1361,23 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 #define PANEL_ENCODER_75FRC_E 0x00 #define PANEL_ENCODER_75FRC_F 0x80 -/**************************************************************************/ - +/****************************************************************************/ +// Structures used by SetVoltageTable +/****************************************************************************/ #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 +#define SET_VOLTAGE_INIT_MODE 5 +#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 -#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 +#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 typedef struct _SET_VOLTAGE_PARAMETERS { @@ -1137,7 +1387,6 @@ typedef struct _SET_VOLTAGE_PARAMETERS UCHAR ucReserved; }SET_VOLTAGE_PARAMETERS; - typedef struct _SET_VOLTAGE_PARAMETERS_V2 { UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ @@ -1145,13 +1394,23 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V2 USHORT usVoltageLevel; // real voltage level }SET_VOLTAGE_PARAMETERS_V2; - typedef struct _SET_VOLTAGE_PS_ALLOCATION { SET_VOLTAGE_PARAMETERS sASICSetVoltage; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; }SET_VOLTAGE_PS_ALLOCATION; +/****************************************************************************/ +// Structures used by TVEncoderControlTable +/****************************************************************************/ +typedef struct _TV_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}TV_ENCODER_CONTROL_PARAMETERS; + typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; @@ -1165,6 +1424,9 @@ typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION #define USHORT void* #endif +/****************************************************************************/ +// Structure used in Data.mtb +/****************************************************************************/ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! @@ -1207,14 +1469,15 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES #define USHORT UTEMP #endif - typedef struct _ATOM_MASTER_DATA_TABLE { ATOM_COMMON_TABLE_HEADER sHeader; ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; }ATOM_MASTER_DATA_TABLE; - +/****************************************************************************/ +// Structure used in MultimediaCapabilityInfoTable +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { ATOM_COMMON_TABLE_HEADER sHeader; @@ -1225,7 +1488,9 @@ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO UCHAR ucHostPortInfo; // Provides host port configuration information }ATOM_MULTIMEDIA_CAPABILITY_INFO; - +/****************************************************************************/ +// Structure used in MultimediaConfigInfoTable +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { ATOM_COMMON_TABLE_HEADER sHeader; @@ -1244,7 +1509,9 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) }ATOM_MULTIMEDIA_CONFIG_INFO; -/****************************Firmware Info Table Definitions**********************/ +/****************************************************************************/ +// Structures used in FirmwareInfoTable +/****************************************************************************/ // usBIOSCapability Defintion: // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; @@ -1459,6 +1726,9 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 +/****************************************************************************/ +// Structures used in IntegratedSystemInfoTable +/****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 #define IGP_CAP_FLAG_AC_CARD 0x4 #define IGP_CAP_FLAG_SDVO_CARD 0x8 @@ -1540,11 +1810,11 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 { ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulReserved1[2]; //must be 0x0 for the reserved + ULONG ulReserved1[2]; //must be 0x0 for the reserved ULONG ulBootUpUMAClock; //in 10kHz unit ULONG ulBootUpSidePortClock; //in 10kHz unit ULONG ulMinSidePortClock; //in 10kHz unit - ULONG ulReserved2[6]; //must be 0x0 for the reserved + ULONG ulReserved2[6]; //must be 0x0 for the reserved ULONG ulSystemConfig; //see explanation below ULONG ulBootUpReqDisplayVector; ULONG ulOtherDisplayMisc; @@ -1567,7 +1837,13 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 USHORT usUMADataReturnTime; USHORT usLinkStatusZeroTime; USHORT usReserved; - ULONG ulReserved3[101]; //must be 0x0 + ULONG ulHighVoltageHTLinkFreq; // in 10Khz + ULONG ulLowVoltageHTLinkFreq; // in 10Khz + USHORT usMaxUpStreamHTLinkWidth; + USHORT usMaxDownStreamHTLinkWidth; + USHORT usMinUpStreamHTLinkWidth; + USHORT usMinDownStreamHTLinkWidth; + ULONG ulReserved3[97]; //must be 0x0 }ATOM_INTEGRATED_SYSTEM_INFO_V2; /* @@ -1576,8 +1852,20 @@ ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is no ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock ulSystemConfig: -Bit[0]: =1 PowerExpress mode =0 Non-PowerExpress mode; -Bit[1]=1: system is running at overdrived engine clock =0:system is not running at overdrived engine clock +Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; +Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state + =0: system boots up at driver control state. Power state depends on PowerPlay table. +Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. +Bit[3]=1: Only one power state(Performance) will be supported. + =0: Multiple power states supported from PowerPlay table. +Bit[4]=1: CLMC is supported and enabled on current system. + =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. + =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. +Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. + =0: Voltage settings is determined by powerplay table. +Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. + =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. @@ -1606,16 +1894,21 @@ ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked; ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 - + usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. -usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -usMinNBVoltage:Voltage regulator dependent PWM value.Set this one to 0x00 if VC without PWM or no VC at all. +usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. +usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. + GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 + PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 + GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. +ulHTLinkFreq: Bootup HT link Frequency in 10Khz. +usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. +usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. -ulHTLinkFreq: Current HT link Frequency in 10Khz. -usMinHTLinkWidth: -usMaxHTLinkWidth: usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us @@ -1624,10 +1917,27 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) + +ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. + This must be less than or equal to ulHTLinkFreq(bootup frequency). +ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. + This must be less than or equal to ulHighVoltageHTLinkFreq. + +usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. +usMaxDownStreamHTLinkWidth: same as above. +usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. +usMinDownStreamHTLinkWidth: same as above. */ + #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 +#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 +#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 +#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 +#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 +#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 +#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF @@ -1683,14 +1993,16 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: #define ATOM_DEVICE_DFP2_INDEX 0x00000007 #define ATOM_DEVICE_CV_INDEX 0x00000008 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 -#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A -#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B +#define ATOM_DEVICE_DFP4_INDEX 0x0000000A +#define ATOM_DEVICE_DFP5_INDEX 0x0000000B #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F -#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2) +#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO +#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) + #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) @@ -1703,9 +2015,11 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) +#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) +#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) #define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT -#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT +#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT #define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT #define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT @@ -1776,7 +2090,6 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: // = 3-7 Reserved for future I2C engines // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C - typedef struct _ATOM_I2C_ID_CONFIG { #if ATOM_BIG_ENDIAN @@ -1797,6 +2110,9 @@ typedef union _ATOM_I2C_ID_CONFIG_ACCESS }ATOM_I2C_ID_CONFIG_ACCESS; +/****************************************************************************/ +// Structure used in GPIO_I2C_InfoTable +/****************************************************************************/ typedef struct _ATOM_GPIO_I2C_ASSIGMENT { USHORT usClkMaskRegisterIndex; @@ -1826,6 +2142,9 @@ typedef struct _ATOM_GPIO_I2C_INFO ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; }ATOM_GPIO_I2C_INFO; +/****************************************************************************/ +// Common Structure used in other structures +/****************************************************************************/ #ifndef _H2INC @@ -1908,7 +2227,9 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW // VESA_BORDER = EDID_BORDER - +/****************************************************************************/ +// Structure used in SetCRTC_UsingDTDTimingTable +/****************************************************************************/ typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { USHORT usH_Size; @@ -1926,6 +2247,9 @@ typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS UCHAR ucPadding[3]; }SET_CRTC_USING_DTD_TIMING_PARAMETERS; +/****************************************************************************/ +// Structure used in SetCRTC_TimingTable +/****************************************************************************/ typedef struct _SET_CRTC_TIMING_PARAMETERS { USHORT usH_Total; // horizontal total @@ -1946,7 +2270,11 @@ typedef struct _SET_CRTC_TIMING_PARAMETERS }SET_CRTC_TIMING_PARAMETERS; #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS - +/****************************************************************************/ +// Structure used in StandardVESA_TimingTable +// AnalogTV_InfoTable +// ComponentVideoInfoTable +/****************************************************************************/ typedef struct _ATOM_MODE_TIMING { USHORT usCRTC_H_Total; @@ -1968,7 +2296,6 @@ typedef struct _ATOM_MODE_TIMING UCHAR ucRefreshRate; }ATOM_MODE_TIMING; - typedef struct _ATOM_DTD_FORMAT { USHORT usPixClk; @@ -1989,12 +2316,19 @@ typedef struct _ATOM_DTD_FORMAT UCHAR ucRefreshRate; }ATOM_DTD_FORMAT; +/****************************************************************************/ +// Structure used in LVDS_InfoTable +// * Need a document to describe this table +/****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 -/****************************LVDS Info Table Definitions **********************/ +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +#define LCDPANEL_CAP_READ_EDID 0x1 + //ucTableFormatRevision=1 //ucTableContentRevision=1 typedef struct _ATOM_LVDS_INFO @@ -2123,9 +2457,9 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; }ATOM_SPREAD_SPECTRUM_INFO; - - - +/****************************************************************************/ +// Structure used in AnalogTV_InfoTable (Top level) +/****************************************************************************/ //ucTVBootUpDefaultStd definiton: //ATOM_TV_NTSC 1 @@ -2137,7 +2471,6 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO //ATOM_TV_PAL60 7 //ATOM_TV_SECAM 8 - //ucTVSuppportedStd definition: #define NTSC_SUPPORT 0x1 #define NTSCJ_SUPPORT 0x2 @@ -2227,7 +2560,15 @@ typedef struct _ATOM_ANALOG_TV_INFO #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 @@ -2240,6 +2581,15 @@ typedef struct _ATOM_ANALOG_TV_INFO #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 +/***********************************************************************************/ +// Structure used in VRAM_UsageByFirmwareTable +// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm +// at running time. +// note2: From RV770, the memory is more than 32bit addressable, so we will change +// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains +// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware +// (in offset to start of memory address) is KB aligned instead of byte aligend. +/***********************************************************************************/ #define... [truncated message content] |
From: <dar...@ke...> - 2009-02-20 05:30:41
|
libdrm/nouveau/nouveau_device.c | 1 libdrm/nouveau/nouveau_dma.c | 1 linux-core/Makefile.kernel | 2 linux-core/nouveau_backlight.c | 35 +++- linux-core/nouveau_bios.c | 28 +-- linux-core/nouveau_bo.c | 17 -- linux-core/nouveau_dma.h | 106 ++++++++++++ linux-core/nouveau_fence.c | 2 linux-core/nouveau_gem.c | 37 +--- linux-core/nv50_connector.c | 2 linux-core/nv50_crtc.c | 12 - linux-core/nv50_cursor.c | 16 - linux-core/nv50_dac.c | 24 +- linux-core/nv50_display.c | 94 +++++------ linux-core/nv50_fbcon.c | 2 linux-core/nv50_fbcon.h | 1 linux-core/nv50_fbcon_accel.c | 216 +++++++++++++++++++++++++ linux-core/nv50_i2c.c | 4 linux-core/nv50_sor.c | 16 - shared-core/nouveau_dma.c | 15 + shared-core/nouveau_dma.h | 2 shared-core/nouveau_drv.h | 53 ++++-- shared-core/nouveau_fifo.c | 142 ++++++++-------- shared-core/nouveau_irq.c | 146 ++++++++--------- shared-core/nouveau_mem.c | 277 +++++++++++++++++++++----------- shared-core/nouveau_object.c | 53 ++++-- shared-core/nouveau_state.c | 337 ++++++++++++++++++---------------------- shared-core/nouveau_swmthd.c | 24 +- shared-core/nv04_fb.c | 2 shared-core/nv04_fifo.c | 44 ++--- shared-core/nv04_graph.c | 78 ++++----- shared-core/nv04_instmem.c | 2 shared-core/nv04_mc.c | 2 shared-core/nv04_timer.c | 16 - shared-core/nv10_fb.c | 4 shared-core/nv10_fifo.c | 68 ++++---- shared-core/nv10_graph.c | 128 +++++++-------- shared-core/nv20_graph.c | 264 +++++++++++++++---------------- shared-core/nv40_fb.c | 14 - shared-core/nv40_fifo.c | 110 ++++++------- shared-core/nv40_graph.c | 242 ++++++++++++++-------------- shared-core/nv40_mc.c | 12 - shared-core/nv50_fifo.c | 58 +++--- shared-core/nv50_graph.c | 60 +++---- shared-core/nv50_instmem.c | 34 ++-- shared-core/nv50_mc.c | 2 46 files changed, 1624 insertions(+), 1181 deletions(-) New commits: commit 8616e8499bc16ebd8e49efe022929d4519bdc44b Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 15:26:24 2009 +1000 nv50: rework vm handling so we can support >512MiB VRAM diff --git a/linux-core/nouveau_bo.c b/linux-core/nouveau_bo.c index e084a4d..1d4d1be 100644 --- a/linux-core/nouveau_bo.c +++ b/linux-core/nouveau_bo.c @@ -296,6 +296,7 @@ nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait, { struct drm_nouveau_private *dev_priv = bo->dev->dev_private; struct drm_bo_mem_reg *old_mem = &bo->mem; + int ret; if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE) return drm_bo_move_memcpy(bo, evict, no_wait, new_mem); @@ -304,9 +305,7 @@ nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait, (new_mem->mem_type == DRM_BO_MEM_VRAM || new_mem->mem_type == DRM_BO_MEM_PRIV0) && !(new_mem->proposed_flags & DRM_NOUVEAU_BO_FLAG_NOVM)) { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = new_mem->mm_node->start << PAGE_SHIFT; - unsigned count = new_mem->size / 65536; + uint64_t offset = new_mem->mm_node->start << PAGE_SHIFT; unsigned tile = 0; if (new_mem->proposed_flags & DRM_NOUVEAU_BO_FLAG_TILE) { @@ -316,13 +315,11 @@ nouveau_bo_move(struct drm_buffer_object *bo, int evict, int no_wait, tile = 0x00007000; } - while (count--) { - unsigned pte = offset / 65536; - - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; - } + ret = nv50_mem_vm_bind_linear(bo->dev, + offset + dev_priv->vm_vram_base, + new_mem->size, tile, offset); + if (ret) + return ret; } if (old_mem->flags & DRM_BO_FLAG_CLEAN) { diff --git a/linux-core/nouveau_gem.c b/linux-core/nouveau_gem.c index bb59999..d290f26 100644 --- a/linux-core/nouveau_gem.c +++ b/linux-core/nouveau_gem.c @@ -662,12 +662,14 @@ nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data, int nouveau_gem_ioctl_tile(struct drm_device *dev, void *data, - struct drm_file *file_priv) + struct drm_file *file_priv) { struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_gem_tile *req = data; struct nouveau_gem_object *ngem; struct drm_gem_object *gem; + unsigned offset, tile = 0; + int ret; NOUVEAU_CHECK_INITIALISED_WITH_RETURN; NOUVEAU_CHECK_MM_ENABLED_WITH_RETURN; @@ -677,30 +679,21 @@ nouveau_gem_ioctl_tile(struct drm_device *dev, void *data, return -EINVAL; ngem = gem->driver_private; - { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = ngem->bo->offset + req->delta; - unsigned count = req->size / 65536; - unsigned tile = 0; - - offset -= dev_priv->vm_vram_base; - - if (req->flags & NOUVEAU_MEM_TILE) { - if (req->flags & NOUVEAU_MEM_TILE_ZETA) - tile = 0x00002800; - else - tile = 0x00007000; - } - - while (count--) { - unsigned pte = offset / 65536; + offset = ngem->bo->offset + req->delta; + offset -= dev_priv->vm_vram_base; - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; - } + if (req->flags & NOUVEAU_MEM_TILE) { + if (req->flags & NOUVEAU_MEM_TILE_ZETA) + tile = 0x00002800; + else + tile = 0x00007000; } + ret = nv50_mem_vm_bind_linear(dev, ngem->bo->offset + req->delta, + req->size, tile, offset); + if (ret) + return ret; + mutex_lock(&dev->struct_mutex); drm_gem_object_unreference(gem); mutex_unlock(&dev->struct_mutex); diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 39a5932..7a4cf58 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -159,7 +159,7 @@ struct nouveau_channel /* NV50 VM */ struct nouveau_gpuobj *vm_pd; struct nouveau_gpuobj_ref *vm_gart_pt; - struct nouveau_gpuobj_ref *vm_vram_pt; + struct nouveau_gpuobj_ref **vm_vram_pt; /* Objects */ struct nouveau_gpuobj_ref *ramin; /* Private instmem */ @@ -320,7 +320,8 @@ struct drm_nouveau_private { uint64_t vm_vram_base; uint64_t vm_vram_size; uint64_t vm_end; - struct nouveau_gpuobj *vm_vram_pt; + struct nouveau_gpuobj **vm_vram_pt; + int vm_vram_pt_nr; /* the mtrr covering the FB */ int fb_mtrr; @@ -441,6 +442,11 @@ extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*); extern int nouveau_mem_init(struct drm_device *); extern int nouveau_mem_init_ttm(struct drm_device *); extern void nouveau_mem_close(struct drm_device *); +extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, + uint32_t size, uint32_t flags, + uint64_t phys); +extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, + uint32_t size); /* nouveau_notifier.c */ extern int nouveau_notifier_init_channel(struct nouveau_channel *); diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 43eca75..5c31224 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -202,6 +202,144 @@ void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap) } /* + * NV50 VM helpers + */ +#define VMBLOCK (512*1024*1024) +static int +nv50_mem_vm_preinit(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + + dev_priv->vm_gart_base = roundup(0, VMBLOCK); + dev_priv->vm_gart_size = VMBLOCK; + + dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size; + dev_priv->vm_vram_size = roundup(nouveau_mem_fb_amount(dev), VMBLOCK); + dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size; + + DRM_DEBUG("NV50VM: GART 0x%016llx-0x%016llx\n", + dev_priv->vm_gart_base, + dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1); + DRM_DEBUG("NV50VM: VRAM 0x%016llx-0x%016llx\n", + dev_priv->vm_vram_base, + dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1); + return 0; +} + +static void +nv50_mem_vm_takedown(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + int i; + + if (!dev_priv->vm_vram_pt) + return; + + for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { + if (!dev_priv->vm_vram_pt[i]) + break; + + nouveau_gpuobj_del(dev, &dev_priv->vm_vram_pt[i]); + } + + drm_free(dev_priv->vm_vram_pt, + dev_priv->vm_vram_pt_nr * sizeof(struct nouveau_gpuobj *), + DRM_MEM_DRIVER); + dev_priv->vm_vram_pt = NULL; + dev_priv->vm_vram_pt_nr = 0; +} + +static int +nv50_mem_vm_init(struct drm_device *dev) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + const int nr = dev_priv->vm_vram_size / VMBLOCK; + int i, ret; + + dev_priv->vm_vram_pt_nr = nr; + dev_priv->vm_vram_pt = drm_calloc(nr, sizeof(struct nouveau_gpuobj *), + DRM_MEM_DRIVER); + if (!dev_priv->vm_vram_pt) + return -ENOMEM; + + for (i = 0; i < nr; i++) { + ret = nouveau_gpuobj_new(dev, NULL, VMBLOCK/65536*8, 0, + NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_ALLOW_NO_REFS, + &dev_priv->vm_vram_pt[i]); + if (ret) { + DRM_ERROR("Error creating VRAM page tables: %d\n", ret); + return ret; + } + } + + return 0; +} + +int +nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, + uint32_t flags, uint64_t phys) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_gpuobj **pgt; + unsigned psz, pfl; + + if (virt >= dev_priv->vm_gart_base && + (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) { + psz = 4096; + pgt = &dev_priv->gart_info.sg_ctxdma; + pfl = 0x21; + virt -= dev_priv->vm_gart_base; + } else + if (virt >= dev_priv->vm_vram_base && + (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) { + psz = 65536; + pgt = dev_priv->vm_vram_pt; + pfl = 0x01; + virt -= dev_priv->vm_vram_base; + } else { + DRM_ERROR("Invalid address: 0x%16llx-0x%16llx\n", + virt, virt + size - 1); + return -EINVAL; + } + + size &= ~(psz - 1); + + if (flags & 0x80000000) { + while (size) { + struct nouveau_gpuobj *pt = pgt[virt / (512*1024*1024)]; + int pte = ((virt % (512*1024*1024)) / psz) * 2; + + INSTANCE_WR(pt, pte++, 0x00000000); + INSTANCE_WR(pt, pte++, 0x00000000); + + size -= psz; + virt += psz; + } + } else { + while (size) { + struct nouveau_gpuobj *pt = pgt[virt / (512*1024*1024)]; + int pte = ((virt % (512*1024*1024)) / psz) * 2; + + INSTANCE_WR(pt, pte++, phys | pfl); + INSTANCE_WR(pt, pte++, flags); + + size -= psz; + phys += psz; + virt += psz; + } + } + + return 0; +} + +void +nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) +{ + nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0); +} + +/* * Cleanup everything */ void nouveau_mem_takedown(struct mem_block **heap) @@ -225,6 +363,9 @@ void nouveau_mem_close(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; + if (dev_priv->card_type >= NV_50) + nv50_mem_vm_takedown(dev); + if (!dev_priv->mm_enabled) { nouveau_mem_takedown(&dev_priv->agp_heap); nouveau_mem_takedown(&dev_priv->fb_heap); @@ -405,21 +546,6 @@ nouveau_mem_init_agp(struct drm_device *dev, int ttm) return 0; } - -static int -nv50_mem_vm_preinit(struct drm_device *dev) -{ - struct drm_nouveau_private *dev_priv = dev->dev_private; - - dev_priv->vm_gart_base = 0; - dev_priv->vm_gart_size = 512 * 1024 * 1024; - dev_priv->vm_vram_base = 512 * 1024 * 1024; - dev_priv->vm_vram_size = 512 * 1024 * 1024; - dev_priv->vm_end = 1024ULL * 1024 * 1024; - - return 0; -} - int nouveau_mem_init_ttm(struct drm_device *dev) { @@ -484,16 +610,10 @@ nouveau_mem_init_ttm(struct drm_device *dev) drm_get_resource_len(dev, 1), DRM_MTRR_WC); - /* G8x: Allocate shared page table to map real VRAM pages into */ if (dev_priv->card_type >= NV_50) { - unsigned size = ((512 * 1024 * 1024) / 65536) * 8; - - ret = nouveau_gpuobj_new(dev, NULL, size, 0, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->vm_vram_pt); + ret = nv50_mem_vm_init(dev); if (ret) { - DRM_ERROR("Error creating VRAM page table: %d\n", ret); + DRM_ERROR("Error creating VM page tables: %d\n", ret); return ret; } } @@ -605,21 +725,14 @@ int nouveau_mem_init(struct drm_device *dev) } } - /* G8x: Allocate shared page table to map real VRAM pages into */ if (dev_priv->card_type >= NV_50) { - unsigned size = ((512 * 1024 * 1024) / 65536) * 8; - - ret = nouveau_gpuobj_new(dev, NULL, size, 0, - NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_ALLOW_NO_REFS, - &dev_priv->vm_vram_pt); + ret = nv50_mem_vm_init(dev); if (ret) { - DRM_ERROR("Error creating VRAM page table: %d\n", ret); + DRM_ERROR("Error creating VM page tables: %d\n", ret); return ret; } } - return 0; } @@ -755,17 +868,9 @@ alloc_ok: /* On G8x, map memory into VM */ if (block->flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50 && !(flags & NOUVEAU_MEM_NOVM)) { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; unsigned offset = block->start - dev_priv->vm_vram_base; - unsigned count = block->size / 65536; unsigned tile = 0; - if (!pt) { - DRM_ERROR("vm alloc without vm pt\n"); - nouveau_mem_free_block(block); - return NULL; - } - /* The tiling stuff is *not* what NVIDIA does - but both the * 2D and 3D engines seem happy with this simpler method. * Should look into why NVIDIA do what they do at some point. @@ -777,12 +882,12 @@ alloc_ok: tile = 0x00007000; } - while (count--) { - unsigned pte = offset / 65536; - - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; + ret = nv50_mem_vm_bind_linear(dev, block->start, block->size, + tile, offset); + if (ret) { + DRM_ERROR("error binding into vm: %d\n", ret); + nouveau_mem_free_block(block); + return NULL; } } else if (block->flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50) { @@ -860,24 +965,9 @@ void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) /* G8x: Remove pages from vm */ if (block->flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50 && !(block->flags & NOUVEAU_MEM_NOVM)) { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = block->start - dev_priv->vm_vram_base; - unsigned count = block->size / 65536; - - if (!pt) { - DRM_ERROR("vm free without vm pt\n"); - goto out_free; - } - - while (count--) { - unsigned pte = offset / 65536; - INSTANCE_WR(pt, (pte * 2) + 0, 0); - INSTANCE_WR(pt, (pte * 2) + 1, 0); - offset += 65536; - } + nv50_mem_vm_unbind(dev, block->start, block->size); } -out_free: nouveau_mem_free_block(block); } @@ -943,6 +1033,8 @@ nouveau_ioctl_mem_tile(struct drm_device *dev, void *data, struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_mem_tile *memtile = data; struct mem_block *block = NULL; + unsigned offset, tile = 0; + int ret; NOUVEAU_CHECK_INITIALISED_WITH_RETURN; NOUVEAU_CHECK_MM_DISABLED_WITH_RETURN; @@ -953,36 +1045,27 @@ nouveau_ioctl_mem_tile(struct drm_device *dev, void *data, if (memtile->flags & NOUVEAU_MEM_FB) block = find_block(dev_priv->fb_heap, memtile->offset); - if (!block) + if (!block || (memtile->delta + memtile->size > block->size)) return -EINVAL; if (block->file_priv != file_priv) return -EPERM; - { - struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt; - unsigned offset = block->start + memtile->delta; - unsigned count = memtile->size / 65536; - unsigned tile = 0; - - offset -= dev_priv->vm_vram_base; + offset = block->start + memtile->delta; + offset -= dev_priv->vm_vram_base; - if (memtile->flags & NOUVEAU_MEM_TILE) { - if (memtile->flags & NOUVEAU_MEM_TILE_ZETA) - tile = 0x00002800; - else - tile = 0x00007000; - } - - while (count--) { - unsigned pte = offset / 65536; - - INSTANCE_WR(pt, (pte * 2) + 0, offset | 1); - INSTANCE_WR(pt, (pte * 2) + 1, 0x00000000 | tile); - offset += 65536; - } + if (memtile->flags & NOUVEAU_MEM_TILE) { + if (memtile->flags & NOUVEAU_MEM_TILE_ZETA) + tile = 0x00002800; + else + tile = 0x00007000; } + ret = nv50_mem_vm_bind_linear(dev, block->start + memtile->delta, + memtile->size, tile, offset); + if (ret) + return ret; + return 0; } diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 74fc3d1..10e715d 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -992,11 +992,11 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, /* NV50 VM * - Allocate per-channel page-directory - * - Point offset 0-512MiB at shared PCIEGART table - * - Point offset 512-1024MiB at shared VRAM table + * - Map GART and VRAM into the channel's address space at the + * locations determined during init. */ if (dev_priv->card_type >= NV_50) { - uint32_t vm_offset; + uint32_t vm_offset, pde; vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200; vm_offset += chan->ramin->gpuobj->im_pramin->start; @@ -1008,21 +1008,35 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe); } - if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0, - dev_priv->gart_info.sg_ctxdma, - &chan->vm_gart_pt))) + pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 2; + ret = nouveau_gpuobj_ref_add(dev, NULL, 0, + dev_priv->gart_info.sg_ctxdma, + &chan->vm_gart_pt); + if (ret) return ret; - INSTANCE_WR(chan->vm_pd, (0+0)/4, + INSTANCE_WR(chan->vm_pd, pde++, chan->vm_gart_pt->instance | 0x03); - INSTANCE_WR(chan->vm_pd, (0+4)/4, 0x00000000); + INSTANCE_WR(chan->vm_pd, pde++, 0x00000000); - if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0, - dev_priv->vm_vram_pt, - &chan->vm_vram_pt))) - return ret; - INSTANCE_WR(chan->vm_pd, (8+0)/4, - chan->vm_vram_pt->instance | 0x61); - INSTANCE_WR(chan->vm_pd, (8+4)/4, 0x00000000); + chan->vm_vram_pt = + drm_calloc(dev_priv->vm_vram_pt_nr, + sizeof(struct nouveau_gpuobj_ref *), + DRM_MEM_DRIVER); + if (!chan->vm_vram_pt) + return -ENOMEM; + + pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 2; + for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { + ret = nouveau_gpuobj_ref_add(dev, NULL, 0, + dev_priv->vm_vram_pt[i], + &chan->vm_vram_pt[i]); + if (ret) + return ret; + + INSTANCE_WR(chan->vm_pd, pde++, + chan->vm_vram_pt[i]->instance | 0x61); + INSTANCE_WR(chan->vm_pd, pde++, 0x00000000); + } } /* RAMHT */ @@ -1100,9 +1114,11 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, void nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) { + struct drm_nouveau_private *dev_priv = chan->dev->dev_private; struct drm_device *dev = chan->dev; struct list_head *entry, *tmp; struct nouveau_gpuobj_ref *ref; + int i; DRM_DEBUG("ch%d\n", chan->id); @@ -1116,7 +1132,12 @@ nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) nouveau_gpuobj_del(dev, &chan->vm_pd); nouveau_gpuobj_ref_del(dev, &chan->vm_gart_pt); - nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt); + if (chan->vm_vram_pt) { + for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) + nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]); + drm_free(chan->vm_vram_pt, dev_priv->vm_vram_pt_nr * + sizeof(struct nouveau_gpuobj_ref *), DRM_MEM_DRIVER); + } if (chan->ramin_heap) nouveau_mem_takedown(&chan->ramin_heap); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index f39a041..22ab688 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -369,8 +369,6 @@ static void nouveau_card_takedown(struct drm_device *dev) nouveau_sgdma_takedown(dev); nouveau_gpuobj_takedown(dev); - nouveau_gpuobj_del(dev, &dev_priv->vm_vram_pt); - nouveau_mem_close(dev); engine->instmem.takedown(dev); commit 3c649c9329eeb0df557d0b7675c5dfb6969bf716 Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 15:23:50 2009 +1000 nouveau: generalise waiting on register status with timeout diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 66660e6..39a5932 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -407,6 +407,8 @@ extern int nouveau_ioctl_getparam(struct drm_device *, void *data, struct drm_file *); extern int nouveau_ioctl_setparam(struct drm_device *, void *data, struct drm_file *); +extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, + uint32_t reg, uint32_t mask, uint32_t val); extern void nouveau_wait_for_idle(struct drm_device *); extern int nouveau_card_init(struct drm_device *); extern int nouveau_ioctl_card_init(struct drm_device *, void *data, @@ -709,6 +711,8 @@ extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, #define nv_wr16(reg,val) nv_out16(dev_priv->mmio, (reg), (val)) #define nv_rd08(reg) nv_in08(dev_priv->mmio, (reg)) #define nv_wr08(reg,val) nv_out08(dev_priv->mmio, (reg), (val)) +#define nv_wait(reg,mask,val) nouveau_wait_until(dev, 1000000000ULL, (reg), \ + (mask), (val)) /* PRAMIN access */ #define nv_ri32(reg) nv_in32(dev_priv->ramin, (reg)) #define nv_wi32(reg,val) nv_out32(dev_priv->ramin, (reg), (val)) diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 7818bcd..f39a041 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -723,33 +723,38 @@ nouveau_ioctl_setparam(struct drm_device *dev, void *data, return 0; } -/* waits for idle */ +/* Wait until (value(reg) & mask) == val, up until timeout has hit */ +bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout, + uint32_t reg, uint32_t mask, uint32_t val) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_timer_engine *ptimer = &dev_priv->Engine.timer; + uint64_t start = ptimer->read(dev); + + do { + if ((nv_rd32(reg) & mask) == val) + return true; + } while (ptimer->read(dev) - start < timeout); + + return false; +} + +/* Waits for PGRAPH to go completely idle */ void nouveau_wait_for_idle(struct drm_device *dev) { struct drm_nouveau_private *dev_priv=dev->dev_private; + bool ret = true; + switch(dev_priv->card_type) { case NV_50: break; - default: { - /* This stuff is more or less a copy of what is seen - * in nv28 kmmio dump. - */ - uint64_t started = dev_priv->Engine.timer.read(dev); - uint64_t stopped = started; - uint32_t status; - do { - uint32_t pmc_e = nv_rd32(NV03_PMC_ENABLE); - (void)pmc_e; - status = nv_rd32(NV04_PGRAPH_STATUS); - if (!status) - break; - stopped = dev_priv->Engine.timer.read(dev); - /* It'll never wrap anyway... */ - } while (stopped - started < 1000000000ULL); - if (status) + default: + ret = nouveau_wait_until(dev, 1000000000ULL, NV04_PGRAPH_STATUS, + 0xFFFFFFFF, 0x00000000); + if (ret) { DRM_ERROR("timed out with status 0x%08x\n", - status); - } + nv_rd32(NV04_PGRAPH_STATUS)); + } } } commit 393494d9bd51b8c4901bc70a339209dcde32c5d1 Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 15:19:42 2009 +1000 nv50: fix some fbcon corruption issues diff --git a/linux-core/nv50_fbcon_accel.c b/linux-core/nv50_fbcon_accel.c index e88fc5f..b067d0d 100644 --- a/linux-core/nv50_fbcon_accel.c +++ b/linux-core/nv50_fbcon_accel.c @@ -6,9 +6,44 @@ static int nv50_fbcon_sync(struct fb_info *info) { - if (info->state != FBINFO_STATE_RUNNING) + struct nv50_fbcon_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_channel *chan = dev_priv->channel; + int ret, i; + + if (info->state != FBINFO_STATE_RUNNING || + info->flags & FBINFO_HWACCEL_DISABLED) return 0; + if (RING_SPACE(chan, 4)) { + DRM_ERROR("GPU lockup - switching to software fbcon\n"); + info->flags |= FBINFO_HWACCEL_DISABLED; + return 0; + } + + BEGIN_RING(chan, 0, 0x0104, 1); + OUT_RING (chan, 0); + BEGIN_RING(chan, 0, 0x0100, 1); + OUT_RING (chan, 0); + chan->m2mf_ntfy_map[3] = 0xffffffff; + FIRE_RING (chan); + + ret = -EBUSY; + for (i = 0; i < 100000; i++) { + if (chan->m2mf_ntfy_map[3] == 0) { + ret = 0; + break; + } + DRM_UDELAY(1); + } + + if (ret) { + DRM_ERROR("GPU lockup - switching to software fbcon\n"); + info->flags |= FBINFO_HWACCEL_DISABLED; + return 0; + } + return 0; } diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c index 276575a..5af1577 100644 --- a/shared-core/nouveau_dma.c +++ b/shared-core/nouveau_dma.c @@ -122,6 +122,17 @@ nouveau_dma_channel_setup(struct nouveau_channel *chan) chan->dma.pushbuf = (void *)chan->pushbuf_mem->map->handle; } + /* Map M2MF notifier object - fbcon. */ + if (drm_core_check_feature(dev, DRIVER_MODESET)) { + ret = drm_bo_kmap(chan->notifier_block->bo, 0, + chan->notifier_block->bo->mem.num_pages, + &chan->notifier_block->kmap); + if (ret) + return ret; + chan->m2mf_ntfy_map = chan->notifier_block->kmap.virtual; + chan->m2mf_ntfy_map += chan->m2mf_ntfy; + } + /* Initialise DMA vars */ chan->dma.max = (chan->pushbuf_mem->size >> 2) - 2; chan->dma.put = 0; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index b0b15a3..66660e6 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -169,6 +169,7 @@ struct nouveau_channel /* GPU object info for stuff used in-kernel (mm_enabled) */ uint32_t m2mf_ntfy; + volatile uint32_t *m2mf_ntfy_map; uint32_t vram_handle; uint32_t gart_handle; commit 6ec57ecae6fc43df8bfc5e96626967fd0cfe6c32 Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 15:04:23 2009 +1000 nouveau: signal any outstanding fences on channel destroy diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index abc710d..e244a89 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -471,6 +471,12 @@ void nouveau_fifo_free(struct nouveau_channel *chan) } } + /* Signal all pending fences, if any */ + if (dev_priv->mm_enabled) { + drm_fence_handler(dev, chan->id, chan->next_sequence, + DRM_FENCE_TYPE_EXE, 0); + } + /*XXX: Maybe should wait for PGRAPH to finish with the stuff it fetched * from CACHE1 too? */ commit 32a7de52a7f4d08521606b3ed17557fb0dd1c69d Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 15:03:07 2009 +1000 nv50: basic fbcon acceleration diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel index 3f84cf1..c25ae7c 100644 --- a/linux-core/Makefile.kernel +++ b/linux-core/Makefile.kernel @@ -40,7 +40,7 @@ nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \ nv04_instmem.o nv50_instmem.o \ nouveau_bios.o \ nv50_crtc.o nv50_cursor.o nv50_lut.o nv50_sor.o nv50_dac.o nv50_connector.o nv50_i2c.o nv50_display.o \ - nv50_fbcon.o + nv50_fbcon.o nv50_fbcon_accel.o radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o radeon_gem.o \ radeon_buffer.o radeon_fence.o atom.o radeon_display.o radeon_atombios.o radeon_i2c.o radeon_connectors.o radeon_cs.o \ atombios_crtc.o radeon_encoders.o radeon_fb.o radeon_combios.o radeon_legacy_crtc.o radeon_legacy_encoders.o \ diff --git a/linux-core/nouveau_dma.h b/linux-core/nouveau_dma.h deleted file mode 120000 index a545e38..0d21609 --- a/linux-core/nouveau_dma.h +++ /dev/null @@ -1 +0,0 @@ -../shared-core/nouveau_dma.h \ No newline at end of file diff --git a/linux-core/nouveau_dma.h b/linux-core/nouveau_dma.h new file mode 100644 index a545e38..0d21609 --- /dev/null +++ b/linux-core/nouveau_dma.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2007 Ben Skeggs. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NOUVEAU_DMA_H__ +#define __NOUVEAU_DMA_H__ + +typedef enum { + NvSubM2MF = 0, + NvSub2D = 1 +} nouveau_subchannel_id_t; + +typedef enum { + NvM2MF = 0x80000001, + NvDmaFB = 0x80000002, + NvDmaTT = 0x80000003, + NvNotify0 = 0x80000004, + Nv2D = 0x80000005, +} nouveau_object_handle_t; + +#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 +#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 +#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 +#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 +#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 +#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 +#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c + +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 +#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 +#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c + +static inline int +RING_SPACE(struct nouveau_channel *chan, int size) +{ + if (chan->dma.free < size) { + int ret; + + ret = nouveau_dma_wait(chan, size); + if (ret) + return ret; + } + + chan->dma.free -= size; + return 0; +} + +static inline void +OUT_RING(struct nouveau_channel *chan, int data) +{ + chan->dma.pushbuf[chan->dma.cur++] = data; +} + +static inline void +BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) +{ + OUT_RING(chan, (subc << 13) | (size << 18) | mthd); +} + +static inline void +FIRE_RING(struct nouveau_channel *chan) +{ + struct drm_nouveau_private *dev_priv = chan->dev->dev_private; + + if (chan->dma.cur == chan->dma.put) + return; + + DRM_MEMORYBARRIER(); + chan->dma.put = chan->dma.cur; + nv_wr32(chan->put, (chan->dma.put << 2) + chan->pushbuf_base); +} + +/* This should allow easy switching to a real fifo in the future. */ +#define OUT_MODE(mthd, val) do { \ + nv50_display_command(dev_priv, mthd, val); \ +} while(0) + +#endif diff --git a/linux-core/nv50_fbcon.c b/linux-core/nv50_fbcon.c index 20aa16f..c0da05e 100644 --- a/linux-core/nv50_fbcon.c +++ b/linux-core/nv50_fbcon.c @@ -577,6 +577,8 @@ int nv50_fbcon_init(struct drm_device *dev) par->dev = dev; par->fb = drm_fb; + nv50_fbcon_accel_init(info); + register_framebuffer(info); DRM_INFO("nv50drmfb initialised\n"); diff --git a/linux-core/nv50_fbcon.h b/linux-core/nv50_fbcon.h index d7347f9..6f56bb2 100644 --- a/linux-core/nv50_fbcon.h +++ b/linux-core/nv50_fbcon.h @@ -35,6 +35,7 @@ struct nv50_fbcon_par { int nv50_fbcon_init(struct drm_device *dev); int nv50_fbcon_destroy(struct drm_device *dev); +int nv50_fbcon_accel_init(struct fb_info *info); #endif /* __NV50_FBCON_H__ */ diff --git a/linux-core/nv50_fbcon_accel.c b/linux-core/nv50_fbcon_accel.c new file mode 100644 index 0000000..e88fc5f --- /dev/null +++ b/linux-core/nv50_fbcon_accel.c @@ -0,0 +1,181 @@ +#include "drmP.h" +#include "nouveau_drv.h" +#include "nouveau_dma.h" +#include "nv50_fbcon.h" + +static int +nv50_fbcon_sync(struct fb_info *info) +{ + if (info->state != FBINFO_STATE_RUNNING) + return 0; + + return 0; +} + +static void +nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +{ + struct nv50_fbcon_par *par = info->par; + struct drm_nouveau_private *dev_priv = par->dev->dev_private; + struct nouveau_channel *chan = dev_priv->channel; + + if (info->state != FBINFO_STATE_RUNNING) + return; + + if (info->flags & FBINFO_HWACCEL_DISABLED) { + cfb_fillrect(info, rect); + return; + } + + if (RING_SPACE(chan, 9)) { + DRM_ERROR("GPU lockup - switching to software fbcon\n"); + + info->flags |= FBINFO_HWACCEL_DISABLED; + cfb_fillrect(info, rect); + return; + } + + BEGIN_RING(chan, NvSub2D, 0x02ac, 1); + OUT_RING (chan, rect->rop == ROP_COPY ? 3 : 1); + BEGIN_RING(chan, NvSub2D, 0x0588, 1); + OUT_RING (chan, rect->color); + BEGIN_RING(chan, NvSub2D, 0x0600, 4); + OUT_RING (chan, rect->dx); + OUT_RING (chan, rect->dy); + OUT_RING (chan, rect->dx + rect->width); + OUT_RING (chan, rect->dy + rect->height); + FIRE_RING (chan); +} + +static void +nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) +{ + struct nv50_fbcon_par *par = info->par; + struct drm_nouveau_private *dev_priv = par->dev->dev_private; + struct nouveau_channel *chan = dev_priv->channel; + + if (info->state != FBINFO_STATE_RUNNING) + return; + + if (info->flags & FBINFO_HWACCEL_DISABLED) { + cfb_copyarea(info, region); + return; + } + + if (RING_SPACE(chan, 17)) { + DRM_ERROR("GPU lockup - switching to software fbcon\n"); + + info->flags |= FBINFO_HWACCEL_DISABLED; + cfb_copyarea(info, region); + return; + } + + BEGIN_RING(chan, NvSub2D, 0x02ac, 1); + OUT_RING (chan, 3); + BEGIN_RING(chan, NvSub2D, 0x0110, 1); + OUT_RING (chan, 0); + BEGIN_RING(chan, NvSub2D, 0x08b0, 12); + OUT_RING (chan, region->dx); + OUT_RING (chan, region->dy); + OUT_RING (chan, region->width); + OUT_RING (chan, region->height); + OUT_RING (chan, 0); + OUT_RING (chan, 1); + OUT_RING (chan, 0); + OUT_RING (chan, 1); + OUT_RING (chan, 0); + OUT_RING (chan, region->sx); + OUT_RING (chan, 0); + OUT_RING (chan, region->sy); + FIRE_RING (chan); +} + +static void +nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) +{ + if (info->state != FBINFO_STATE_RUNNING) + return; + + if (info->flags & FBINFO_HWACCEL_DISABLED) { + cfb_imageblit(info, image); + return; + } + + cfb_imageblit(info, image); +} + +int +nv50_fbcon_accel_init(struct fb_info *info) +{ + struct nv50_fbcon_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_channel *chan = dev_priv->channel; + struct nouveau_gpuobj *eng2d = NULL; + int ret, format; + + switch (info->var.bits_per_pixel) { + case 16: + format = 0xe8; + break; + default: + format = 0xe6; + break; + } + + ret = nouveau_gpuobj_gr_new(dev_priv->channel, 0x502d, &eng2d); + if (ret) + return ret; + + ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, Nv2D, eng2d, NULL); + if (ret) + return ret; + + ret = RING_SPACE(chan, 34); + if (ret) { + DRM_ERROR("GPU lockup - switching to software fbcon\n"); + return ret; + } + + BEGIN_RING(chan, NvSub2D, 0x0000, 1); + OUT_RING (chan, Nv2D); + BEGIN_RING(chan, NvSub2D, 0x0180, 4); + OUT_RING (chan, NvNotify0); + OUT_RING (chan, chan->vram_handle); + OUT_RING (chan, chan->vram_handle); + OUT_RING (chan, chan->vram_handle); + BEGIN_RING(chan, NvSub2D, 0x0290, 1); + OUT_RING (chan, 0); + BEGIN_RING(chan, NvSub2D, 0x0888, 1); + OUT_RING (chan, 1); + BEGIN_RING(chan, NvSub2D, 0x02a0, 1); + OUT_RING (chan, 0x55); + BEGIN_RING(chan, NvSub2D, 0x0580, 2); + OUT_RING (chan, 4); + OUT_RING (chan, format); + BEGIN_RING(chan, NvSub2D, 0x0200, 2); + OUT_RING (chan, format); + OUT_RING (chan, 1); + BEGIN_RING(chan, NvSub2D, 0x0214, 5); + OUT_RING (chan, info->fix.line_length); + OUT_RING (chan, info->var.xres_virtual); + OUT_RING (chan, info->var.yres_virtual); + OUT_RING (chan, 0); + OUT_RING (chan, info->fix.smem_start - dev_priv->fb_phys); + BEGIN_RING(chan, NvSub2D, 0x0230, 2); + OUT_RING (chan, format); + OUT_RING (chan, 1); + BEGIN_RING(chan, NvSub2D, 0x0244, 5); + OUT_RING (chan, info->fix.line_length); + OUT_RING (chan, info->var.xres_virtual); + OUT_RING (chan, info->var.yres_virtual); + OUT_RING (chan, 0); + OUT_RING (chan, info->fix.smem_start - dev_priv->fb_phys); + + info->fbops->fb_fillrect = nv50_fbcon_fillrect; + info->fbops->fb_copyarea = nv50_fbcon_copyarea; + info->fbops->fb_imageblit = nv50_fbcon_imageblit; + info->fbops->fb_sync = nv50_fbcon_sync; + return 0; +} + commit 776d4fe69743e5cbfece0e0264b9d5ba8af7248e Author: Ben Skeggs <bs...@re...> Date: Fri Feb 20 14:57:40 2009 +1000 nouveau: use consistant register access macros We had quite a variety, name them all similarly and add a few new ones that'll be needed for modesetting. diff --git a/linux-core/nouveau_backlight.c b/linux-core/nouveau_backlight.c index 51c747a..e5aa9e0 100644 --- a/linux-core/nouveau_backlight.c +++ b/linux-core/nouveau_backlight.c @@ -43,7 +43,7 @@ static int nv40_get_intensity(struct backlight_device *bd) { struct drm_device *dev = bl_get_data(bd); struct drm_nouveau_private *dev_priv = dev->dev_private; - int val = (NV_READ(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16; + int val = (nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16; return val; } @@ -53,9 +53,9 @@ static int nv40_set_intensity(struct backlight_device *bd) struct drm_device *dev = bl_get_data(bd); struct drm_nouveau_private *dev_priv = dev->dev_private; int val = bd->props.brightness; - int reg = NV_READ(NV40_PMC_BACKLIGHT); + int reg = nv_rd32(NV40_PMC_BACKLIGHT); - NV_WRITE(NV40_PMC_BACKLIGHT, + nv_wr32(NV40_PMC_BACKLIGHT, (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK)); return 0; @@ -74,7 +74,7 @@ static int nv50_get_intensity(struct backlight_device *bd) struct drm_device *dev = bl_get_data(bd); struct drm_nouveau_private *dev_priv = dev->dev_private; - return NV_READ(NV50_PDISPLAY_BACKLIGHT); + return nv_rd32(NV50_PDISPLAY_BACKLIGHT); } static int nv50_set_intensity(struct backlight_device *bd) @@ -83,7 +83,7 @@ static int nv50_set_intensity(struct backlight_device *bd) struct drm_nouveau_private *dev_priv = dev->dev_private; int val = bd->props.brightness; - NV_WRITE(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE); + nv_wr32(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE); return 0; } @@ -101,7 +101,7 @@ static int nouveau_nv40_backlight_init(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct backlight_device *bd; - if (!(NV_READ(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) + if (!(nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) return 0; bd = backlight_device_register("nv_backlight", &dev->pdev->dev, dev, @@ -122,7 +122,7 @@ static int nouveau_nv50_backlight_init(struct drm_device *dev) struct drm_nouveau_private *dev_priv = dev->dev_private; struct backlight_device *bd; - if (!NV_READ(NV50_PDISPLAY_BACKLIGHT)) + if (!nv_rd32(NV50_PDISPLAY_BACKLIGHT)) return 0; bd = backlight_device_register("nv_backlight", &dev->pdev->dev, dev, diff --git a/linux-core/nouveau_bios.c b/linux-core/nouveau_bios.c index faa2b2b..bcbedb7 100644 --- a/linux-core/nouveau_bios.c +++ b/linux-core/nouveau_bios.c @@ -69,20 +69,20 @@ static void nv_shadow_bios_rom(struct drm_device *dev, uint8_t *data) int i; /* enable access to rom */ - NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED); + nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED); /* This is also valid for pre-NV50, it just happened to be the only define already present. */ for (i=0; i < NV50_PROM__ESIZE; i++) { /* Appearantly needed for a 6600GT/6800LE bug. */ - data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i); - data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i); - data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i); - data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i); - data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i); + data[i] = nv_rd08(NV50_PROM + i); + data[i] = nv_rd08(NV50_PROM + i); + data[i] = nv_rd08(NV50_PROM + i); + data[i] = nv_rd08(NV50_PROM + i); + data[i] = nv_rd08(NV50_PROM + i); } /* disable access to rom */ - NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); + nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); } static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data) @@ -93,20 +93,20 @@ static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data) /* Move the bios copy to the start of ramin? */ if (dev_priv->card_type >= NV_50) { - uint32_t vbios_vram = (NV_READ(0x619f04) & ~0xff) << 8; + uint32_t vbios_vram = (nv_rd32(0x619f04) & ~0xff) << 8; if (!vbios_vram) - vbios_vram = (NV_READ(0x1700) << 16) + 0xf0000; + vbios_vram = (nv_rd32(0x1700) << 16) + 0xf0000; - old_bar0_pramin = NV_READ(0x1700); - NV_WRITE(0x1700, vbios_vram >> 16); + old_bar0_pramin = nv_rd32(0x1700); + nv_wr32(0x1700, vbios_vram >> 16); } for (i=0; i < NV50_PROM__ESIZE; i++) - data[i] = DRM_READ8(dev_priv->mmio, NV04_PRAMIN + i); + data[i] = nv_rd08(NV04_PRAMIN + i); if (dev_priv->card_type >= NV_50) - NV_WRITE(0x1700, old_bar0_pramin); + nv_wr32(0x1700, old_bar0_pramin); } static bool nv_shadow_bios(struct drm_device *dev, uint8_t *data) @@ -640,7 +640,7 @@ bool get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lim if (bios->chip_version > 0x10 && bios->chip_version != 0x15 && bios->chip_version != 0x1a && bios->chip_version != 0x20) crystal_strap_mask |= 1 << 22; - crystal_straps = NV_READ(NV50_PEXTDEV + 0x0) & crystal_strap_mask; + crystal_straps = nv_rd32(NV50_PEXTDEV + 0x0) & crystal_strap_mask; switch (pll_lim_ver) { /* we use version 0 to indicate a pre limit table bios (single stage pll) diff --git a/linux-core/nouveau_fence.c b/linux-core/nouveau_fence.c index 3529bff..26f98c0 100644 --- a/linux-core/nouveau_fence.c +++ b/linux-core/nouveau_fence.c @@ -93,7 +93,7 @@ nouveau_fence_poll(struct drm_device *dev, uint32_t class, uint32_t waiting_type } if (1) { - uint32_t sequence = NV_READ(chan->ref_cnt); + uint32_t sequence = nv_rd32(chan->ref_cnt); DRM_DEBUG("got 0x%08x\n", sequence); drm_fence_handler(dev, class, sequence, waiting_types, 0); diff --git a/linux-core/nv50_connector.c b/linux-core/nv50_connector.c index 9836e1b..16ab7fb 100644 --- a/linux-core/nv50_connector.c +++ b/linux-core/nv50_connector.c @@ -111,7 +111,7 @@ static int nv50_connector_hpd_detect(struct nv50_connector *connector) } /* Check hotplug pins. */ - reg = NV_READ(NV50_PCONNECTOR_HOTPLUG_STATE); + reg = nv_rd32(NV50_PCONNECTOR_HOTPLUG_STATE); if (reg & (NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 << (4 * connector->i2c_chan->index))) present = 1; diff --git a/linux-core/nv50_crtc.c b/linux-core/nv50_crtc.c index 009219a..37b0555 100644 --- a/linux-core/nv50_crtc.c +++ b/linux-core/nv50_crtc.c @@ -401,12 +401,12 @@ static int nv50_crtc_set_clock(struct nv50_crtc *crtc) uint32_t N1 = 0, N2 = 0, M1 = 0, M2 = 0, log2P = 0; - uint32_t reg1 = NV_READ(pll_reg + 4); - uint32_t reg2 = NV_READ(pll_reg + 8); + uint32_t reg1 = nv_rd32(pll_reg + 4); + uint32_t reg2 = nv_rd32(pll_reg + 8); DRM_DEBUG("\n"); - NV_WRITE(pll_reg, NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED | 0x10000011); + nv_wr32(pll_reg, NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED | 0x10000011); /* The other bits are typically empty, but let's be on the safe side. */ reg1 &= 0xff00ff00; @@ -420,8 +420,8 @@ static int nv50_crtc_set_clock(struct nv50_crtc *crtc) reg1 |= (M1 << 16) | N1; reg2 |= (log2P << 28) | (M2 << 16) | N2; - NV_WRITE(pll_reg + 4, reg1); - NV_WRITE(pll_reg + 8, reg2); + nv_wr32(pll_reg + 4, reg1); + nv_wr32(pll_reg + 8, reg2); return 0; } @@ -433,7 +433,7 @@ static int nv50_crtc_set_clock_mode(struct nv50_crtc *crtc) DRM_DEBUG("\n"); /* This acknowledges a clock request. */ - NV_WRITE(NV50_PDISPLAY_CRTC_CLK_CLK_CTRL2(crtc->index), 0); + nv_wr32(NV50_PDISPLAY_CRTC_CLK_CLK_CTRL2(crtc->index), 0); return 0; } diff --git a/linux-core/nv50_cursor.c b/linux-core/nv50_cursor.c index f0ac73b..073b407 100644 --- a/linux-core/nv50_cursor.c +++ b/linux-core/nv50_cursor.c @@ -34,11 +34,11 @@ static int nv50_cursor_enable(struct nv50_crtc *crtc) DRM_DEBUG("\n"); - NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0x2000); - while(NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK); + nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0x2000); + while(nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK); - NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); - while((NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK) + nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); + while((nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK) != NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE); crtc->cursor->enabled = true; @@ -52,8 +52,8 @@ static int nv50_cursor_disable(struct nv50_crtc *crtc) DRM_DEBUG("\n"); - NV_WRITE(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0); - while(NV_READ(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK); + nv_wr32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index), 0); + while(nv_rd32(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(crtc->index)) & NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK); crtc->cursor->enabled = false; @@ -98,9 +98,9 @@ static int nv50_cursor_set_pos(struct nv50_crtc *crtc, int x, int y) { struct drm_nouveau_private *dev_priv = crtc->base.dev->dev_private; - NV_WRITE(NV50_HW_CURSOR_POS(crtc->index), ((y & 0xFFFF) << 16) | (x & 0xFFFF)); + nv_wr32(NV50_HW_CURSOR_POS(crtc->index), ((y & 0xFFFF) << 16) | (x & 0xFFFF)); /* Needed to make the cursor move. */ - NV_WRITE(NV50_HW_CURSOR_POS_CTRL(crtc->index), 0); + nv_wr32(NV50_HW_CURSOR_POS_CTRL(crtc->index), 0); return 0; } diff --git a/linux-core/nv50_dac.c b/linux-core/nv50_dac.c index 0404aac..4cd1a05 100644 --- a/linux-core/nv50_dac.c +++ b/linux-core/nv50_dac.c @@ -92,7 +92,7 @@ static int nv50_dac_set_clock_mode(struct nv50_output *output) DRM_DEBUG("or %d\n", output->or); - NV_WRITE(NV50_PDISPLAY_DAC_CLK_CLK_CTRL2(output->or), 0); + nv_wr32(NV50_PDISPLAY_DAC_CLK_CLK_CTRL2(output->or), 0); return 0; } @@ -106,9 +106,9 @@ static int nv50_dac_set_power_mode(struct nv50_output *output, int mode) DRM_DEBUG("or %d\n", or); /* wait for it to be done */ - while (NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); + while (nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); - val = NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & ~0x7F; + val = nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & ~0x7F; if (mode != DRM_MODE_DPMS_ON) val |= NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_BLANKED; @@ -129,7 +129,7 @@ static int nv50_dac_set_power_mode(struct nv50_output *output, int mode) break; } - NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); + nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); return 0; } @@ -141,11 +141,11 @@ static int nv50_dac_detect(struct nv50_output *output) uint32_t dpms_state, load_pattern, load_state; int or = output->or; - NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(or), 0x00000001); - dpms_state = NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)); + nv_wr32(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(or), 0x00000001); + dpms_state = nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)); - NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), 0x00150000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); - while (NV_READ(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); + nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), 0x00150000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); + while (nv_rd32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); /* Use bios provided value if possible. */ if (dev_priv->bios.dactestval) { @@ -156,12 +156,12 @@ static int nv50_dac_detect(struct nv50_output *output) DRM_DEBUG("Using default load_pattern of %d\n", load_pattern); } - NV_WRITE(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_ACTIVE | load_pattern); + nv_wr32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_ACTIVE | load_pattern); udelay(10000); /* give it some time to process */ - load_state = NV_READ(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or)); + load_state = nv_rd32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or)); - NV_WRITE(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), 0); - NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), dpms_state); + nv_wr32(NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(or), 0); + nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(or), dpms_state); if ((load_state & NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT) == NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT) present = 1; diff --git a/linux-core/nv50_display.c b/linux-core/nv50_display.c index e0f9587..5500e20 100644 --- a/linux-core/nv50_display.c +++ b/linux-core/nv50_display.c @@ -40,46 +40,46 @@ static int nv50_display_pre_init(struct nv50_display *display) DRM_DEBUG("\n"); - NV_WRITE(0x00610184, NV_READ(0x00614004)); + nv_wr32(0x00610184, nv_rd32(0x00614004)); /* * I think the 0x006101XX range is some kind of main control area that enables things. */ /* CRTC? */ - NV_WRITE(0x00610190 + 0 * 0x10, NV_READ(0x00616100 + 0 * 0x800)); - NV_WRITE(0x00610190 + 1 * 0x10, NV_READ(0x00616100 + 1 * 0x800)); - NV_WRITE(0x00610194 + 0 * 0x10, NV_READ(0x00616104 + 0 * 0x800)); - NV_WRITE(0x00610194 + 1 * 0x10, NV_READ(0x00616104 + 1 * 0x800)); - NV_WRITE(0x00610198 + 0 * 0x10, NV_READ(0x00616108 + 0 * 0x800)); - NV_WRITE(0x00610198 + 1 * 0x10, NV_READ(0x00616108 + 1 * 0x800)); - NV_WRITE(0x0061019c + 0 * 0x10, NV_READ(0x0061610c + 0 * 0x800)); - NV_WRITE(0x0061019c + 1 * 0x10, NV_READ(0x0061610c + 1 * 0x800)); + nv_wr32(0x00610190 + 0 * 0x10, nv_rd32(0x00616100 + 0 * 0x800)); + nv_wr32(0x00610190 + 1 * 0x10, nv_rd32(0x00616100 + 1 * 0x800)); + nv_wr32(0x00610194 + 0 * 0x10, nv_rd32(0x00616104 + 0 * 0x800)); + nv_wr32(0x00610194 + 1 * 0x10, nv_rd32(0x00616104 + 1 * 0x800)); + nv_wr32(0x00610198 + 0 * 0x10, nv_rd32(0x00616108 + 0 * 0x800)); + nv_wr32(0x00610198 + 1 * 0x10, nv_rd32(0x00616108 + 1 * 0x800)); + nv_wr32(0x0061019c + 0 * 0x10, nv_rd32(0x0061610c + 0 * 0x800)); + nv_wr32(0x0061019c + 1 * 0x10, nv_rd32(0x0061610c + 1 * 0x800)); /* DAC */ - NV_WRITE(0x006101d0 + 0 * 0x4, NV_READ(0x0061a000 + 0 * 0x800)); - NV_WRITE(0x006101d0 + 1 * 0x4, NV_READ(0x0061a000 + 1 * 0x800)); - NV_WRITE(0x006101d0 + 2 * 0x4, NV_READ(0x0061a000 + 2 * 0x800)); + nv_wr32(0x006101d0 + 0 * 0x4, nv_rd32(0x0061a000 + 0 * 0x800)); + nv_wr32(0x006101d0 + 1 * 0x4, nv_rd32(0x0061a000 + 1 * 0x800)); + nv_wr32(0x006101d0 + 2 * 0x4, nv_rd32(0x0061a000 + 2 * 0x800)); /* SOR */ - NV_WRITE(0x006101e0 + 0 * 0x4, NV_READ(0x0061c000 + 0 * 0x800)); - NV_WRITE(0x006101e0 + 1 * 0x4, NV_READ(0x0061c000 + 1 * 0x800)); + nv_wr32(0x006101e0 + 0 * 0x4, nv_rd32(0x0061c000 + 0 * 0x800)); + nv_wr32(0x006101e0 + 1 * 0x4, nv_rd32(0x0061c000 + 1 * 0x800)); /* Something not yet in use, tv-out maybe. */ - NV_WRITE(0x006101f0 + 0 * 0x4, NV_READ(0x0061e000 + 0 * 0x800)); - NV_WRITE(0x006101f0 + 1 * 0x4, NV_READ(0x0061e000 + 1 * 0x800)); - NV_WRITE(0x006101f0 + 2 * 0x4, NV_READ(0x0061e000 + 2 * 0x800)); + nv_wr32(0x006101f0 + 0 * 0x4, nv_rd32(0x0061e000 + 0 * 0x800)); + nv_wr32(0x006101f0 + 1 * 0x4, nv_rd32(0x0061e000 + 1 * 0x800)); + nv_wr32(0x006101f0 + 2 * 0x4, nv_rd32(0x0061e000 + 2 * 0x800)); for (i = 0; i < 3; i++) { - NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); - NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001); + nv_wr32(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING); + nv_wr32(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001); } /* This used to be in crtc unblank, but seems out of place there. */ - NV_WRITE(NV50_PDISPLAY_UNK_380, 0); + nv_wr32(NV50_PDISPLAY_UNK_380, 0); /* RAM is clamped to 256 MiB. */ ram_amount = nouveau_mem_fb_amount(display->dev); DRM_DEBUG("ram_amount %d\n", ram_amount); if (ram_amount > 256*1024*1024) ram_amount = 256*1024*1024; - NV_WRITE(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); - NV_WRITE(NV50_PDISPLAY_UNK_388, 0x150000); - NV_WRITE(NV50_PDISPLAY_UNK_38C, 0); + nv_wr32(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1); + nv_wr32(NV50_PDISPLAY_UNK_388, 0x150000); + nv_wr32(NV50_PDISPLAY_UNK_38C, 0); display->preinit_done = true; @@ -95,26 +95,26 @@ static int nv50_display_init(struct nv50_display *display) DRM_DEBUG("\n"); /* The precise purpose is unknown, i suspect it has something to do with text mode. */ - if (NV_READ(NV50_PDISPLAY_SUPERVISOR) & 0x100) { - NV_WRITE(NV50_PDISPLAY_SUPERVISOR, 0x100); - NV_WRITE(0x006194e8, NV_READ(0x006194e8) & ~1); - while (NV_READ(0x006194e8) & 2); + if (nv_rd32(NV50_PDISPLAY_SUPERVISOR) & 0x100) { + nv_wr32(NV50_PDISPLAY_SUPERVISOR, 0x100); + nv_wr32(0x006194e8, nv_rd32(0x006194e8) & ~1); + while (nv_rd32(0x006194e8) & 2); } /* taken from nv bug #12637 */ - NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x2b00); + nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0x2b00); do { - val = NV_READ(NV50_PDISPLAY_UNK200_CTRL); + val = nv_rd32(NV50_PDISPLAY_UNK200_CTRL); if ((val & 0x9f0000) == 0x20000) - NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000); + nv_wr32(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000); if ((val & 0x3f0000) == 0x30000) - NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000); + nv_wr32(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000); } while (val & 0x1e0000); - NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE); - NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03); - while (!(NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000)); + nv_wr32(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE); + nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03); + while (!(nv_rd32(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000)); /* For the moment this is just a wrapper, which should be replaced with a real fifo at some point. */ OUT_MODE(NV50_UNK84, 0); @@ -125,10 +125,10 @@ static int nv50_display_init(struct nv50_display *display) OUT_MODE(NV50_CRTC0_UNK82C, 0); /* enable clock change interrupts. */ - NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70); + nv_wr32(NV50_PDISPLAY_SUPERVISOR_INTR, nv_rd32(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70); /* enable hotplug interrupts */ - NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0x7FFF7FFF); + nv_wr32(NV50_PCONNECTOR_HOTPLUG_INTR, 0x7FFF7FFF); display->init_done = true; @@ -164,24 +164,24 @@ static int nv50_display_disable(struct nv50_display *display) else mask = NV50_PDISPLAY_SUPERVISOR_CRTC0; - NV_WRITE(NV50_PDISPLAY_SUPERVISOR, mask); - while (!(NV_READ(NV50_PDISPLAY_SUPERVISOR) & mask)); + nv_wr32(NV50_PDISPLAY_SUPERVISOR, mask); + while (!(nv_rd32(NV50_PDISPLAY_SUPERVISOR) & mask)); } } - NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0); - NV_WRITE(NV50_PDISPLAY_CTRL_STATE, 0); - while ((NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0); + nv_wr32(NV50_PDISPLAY_UNK200_CTRL, 0); + nv_wr32(NV50_PDISPLAY_CTRL_STATE, 0); + while ((nv_rd32(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0); for (i = 0; i < 2; i++) { - while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT); + while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT); } /* disable clock change interrupts. */ - NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70); + nv_wr32(NV50_PDISPLAY_SUPERVISOR_INTR, nv_rd32(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70); /* disable hotplug interrupts */ - NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0); + nv_wr32(NV50_PCONNECTOR_HOTPLUG_INTR, 0); display->init_done = false; @@ -415,12 +415,12 @@ void nv50_display_command(struct drm_nouveau_private *dev_priv, DRM_DEBUG("mthd 0x%03X val 0x%08X\n", mthd, val); - NV_WRITE(NV50_PDISPLAY_CTRL_VAL, val); - NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING | + nv_wr32(NV50_PDISPLAY_CTRL_VAL, val); + nv_wr32(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING | NV50_PDISPLAY_CTRL_STATE_ENABLE | 0x10000 | mthd); - while (NV_READ(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) { + while (nv_rd32(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) { counter++; if (counter > 1000000) { DRM_ERROR("You probably need a reboot now\n"); diff --git a/linux-core/nv50_i2c.c b/linux-core/nv50_i2c.c index 30e317c..7a91873 100644 --- a/linux-core/nv50_i2c.c +++ b/linux-core/nv50_i2c.c @@ -71,7 +71,7 @@ static void nv50_i2c_set_bits(struct nv50_i2c_channel *chan, int clock_high, int if (!port) return; - NV_WRITE(port, 4 | (data_high << 1) | clock_high); + nv_wr32(port, 4 | (data_high << 1) | clock_high); } static void nv50_i2c_get_bits(struct nv50_i2c_channel *chan, int *clock_high, int *data_high) @@ -83,7 +83,7 @@ static void nv50_i2c_get_bits(struct nv50_i2c_channel *chan, int *clock_high, in if (!port) return; - val = NV_READ(port); + val = nv_rd32(port); if (val & 1) *clock_high = 1; diff --git a/linux-core/nv50_sor.c b/linux-core/nv50_sor.c index 544af86..42d39a5 100644 --- a/linux-core/nv50_sor.c +++ b/linux-core/nv50_sor.c @@ -109,7 +109,7 @@ static int nv50_sor_set_clock_mode(struct nv50_output *output) /* 0x70000 was a late addition to nv, mentioned as fixing tmds initialisation on certain gpu's. */ /* I presume it's some kind of clock setting, but what precisely i do not know. */ - NV_WRITE(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0)); + nv_wr32(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0)); return 0; } @@ -123,16 +123,16 @@ static int nv50_sor_set_power_mode(struct nv50_output *output, int mode) DRM_DEBUG("or %d\n", output->or); /* wait for it to be done */ - while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING); + while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING); - val = NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)); + val = nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)); if (mode == DRM_MODE_DPMS_ON) val |= NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON; else val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON; - NV_WRITE(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING); + nv_wr32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING); return 0; } @@ -207,10 +207,10 @@ int nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) if (output->base.encoder_type == DRM_MODE_ENCODER_TMDS) { int or = output->or; - NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700); - NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f); - NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_014(or), 0x00000000); - NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_018(or), 0x00245af8); + nv_wr32... [truncated message content] |