From: <ai...@ke...> - 2006-08-26 23:00:07
|
shared-core/drm_pciids.txt | 208 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 208 insertions(+) New commits: diff-tree 88928380c87e60d22a0a9698c468036f180f0761 (from fef9b30a2b437c0103c33443566604027529b91d) Author: Dave Airlie <ai...@li...> Date: Sun Aug 27 08:59:50 2006 +1000 add pci ids for nouveau diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 9ef2c00..9f42195 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -461,3 +461,211 @@ 0x10DE 0x009C NV40 "NVidia 0x009C" 0x10DE 0x009D NV40 "NVidia Quadro FX 4500" 0x10DE 0x009E NV40 "NVidia 0x009E" + +[nouveau] +0x12d2 0x0008 NV_01 "NV1" +0x12d2 0x0009 NV_01 "DAC64" +0x12d2 0x0018 NV_03 "Riva128" +0x12d2 0x0019 NV_03 "Riva128ZX" +0x12d2 0x0020 NV_04 "TNT" +0x12d2 0x0028 NV_05 "TNT2" +0x12d2 0x0029 NV_05 "UTNT2" +0x12d2 0x002c NV_05 "VTNT2" +0x12d2 0x00a0 NV_05 "ITNT2" +0x10de 0x0020 NV_04 "RIVA TNT" +0x10de 0x0028 NV_05 "RIVA TNT2/TNT2 Pro" +0x10de 0x00a0 NV_05 "Aladdin TNT2" +0x10de 0x002c NV_05 "Vanta/Vanta LT" +0x10de 0x0029 NV_05 "RIVA TNT2 Ultra" +0x10de 0x002d NV_05 "RIVA TNT2 Model 64/Model 64 Pro" +0x10de 0x0100 NV_10 "GeForce 256" +0x10de 0x0101 NV_10 "GeForce DDR" +0x10de 0x0103 NV_10 "Quadro" +0x10de 0x0110 NV_10 "GeForce2 MX/MX 400" +0x10de 0x0111 NV_10 "GeForce2 MX 100/200" +0x10de 0x0113 NV_10 "Quadro2 MXR/EX/Go" +0x10de 0x01a0 NV_10|NV_NFORCE "GeForce2 Integrated GPU" +0x10de 0x0150 NV_10 "GeForce2 GTS/GeForce2 Pro" +0x10de 0x0151 NV_10 "GeForce2 Ti" +0x10de 0x0152 NV_10 "GeForce2 Ultra" +0x10de 0x0153 NV_10 "Quadro2 Pro" +0x10de 0x0170 NV_10 "GeForce4 MX 460" +0x10de 0x0171 NV_10 "GeForce4 MX 440" +0x10de 0x0172 NV_10 "GeForce4 MX 420" +0x10de 0x0173 NV_10 "GeForce4 MX 440-SE" +0x10de 0x0178 NV_20 "Quadro4 550 XGL" +0x10de 0x017a NV_10 "Quadro NVS" +0x10de 0x0181 NV_10 "GeForce4 MX 440 with AGP8X" +0x10de 0x0182 NV_10 "GeForce4 MX 440SE with AGP8X" +0x10de 0x0183 NV_10 "GeForce4 MX 420 with AGP8X" +0x10de 0x0185 NV_10 "GeForce4 MX 4000" +0x10de 0x0188 NV_20 "Quadro4 580 XGL" +0x10de 0x018a NV_10 "Quadro NVS with AGP8X" +0x10de 0x018b NV_20 "Quadro4 380 XGL" +0x10de 0x018c NV_10 "Quadro NVS 50 PCI" +0x10de 0x01f0 NV_10|NV_NFORCE2 "GeForce4 MX Integrated GPU" +0x10de 0x0200 NV_20 "GeForce3" +0x10de 0x0201 NV_20 "GeForce3 Ti 200" +0x10de 0x0202 NV_20 "GeForce3 Ti 500" +0x10de 0x0203 NV_10 "Quadro DCC" +0x10de 0x0250 NV_20 "GeForce4 Ti 4600" +0x10de 0x0251 NV_20 "GeForce4 Ti 4400" +0x10de 0x0252 NV_20 "NV25" +0x10de 0x0253 NV_20 "GeForce4 Ti 4200" +0x10de 0x0258 NV_20 "Quadro4 900 XGL" +0x10de 0x0259 NV_20 "Quadro4 750 XGL" +0x10de 0x025b NV_20 "Quadro4 700 XGL" +0x10de 0x0280 NV_20 "GeForce4 Ti 4800" +0x10de 0x0281 NV_20 "GeForce4 Ti 4200 with AGP8X" +0x10de 0x0282 NV_20 "GeForce4 Ti 4800 SE" +0x10de 0x0288 NV_20 "Quadro4 980 XGL" +0x10de 0x0289 NV_20 "Quadro4 780 XGL" +0x10de 0x0301 NV_30 "GeForce FX 5800 Ultra" +0x10de 0x0302 NV_30 "GeForce FX 5800" +0x10de 0x0308 NV_30 "Quadro FX 2000" +0x10de 0x0309 NV_30 "Quadro FX 1000" +0x10de 0x0311 NV_30 "GeForce FX 5600 Ultra" +0x10de 0x0312 NV_30 "GeForce FX 5600" +0x10de 0x0313 NV_30 "NV31" +0x10de 0x0314 NV_30 "GeForce FX 5600XT" +0x10de 0x0320 NV_30 "GeForce FX 5200" +0x10de 0x0321 NV_30 "GeForce FX 5200 Ultra" +0x10de 0x0322 NV_30 "GeForce FX 5200" +0x10de 0x0323 NV_30 "GeForce FX 5200LE" +0x10de 0x0326 NV_30 "GeForce FX 5500" +0x10de 0x0327 NV_30 "GeForce FX 5100" +0x10de 0x032a NV_10 "Quadro NVS 280 PCI" +0x10de 0x032b NV_30 "Quadro FX 500/FX 600" +0x10de 0x032f NV_30 "NV34GL" +0x10de 0x0330 NV_30 "GeForce FX 5900 Ultra" +0x10de 0x0331 NV_30 "GeForce FX 5900" +0x10de 0x0332 NV_30 "GeForce FX 5900XT" +0x10de 0x0333 NV_30 "GeForce FX 5950 Ultra" +0x10de 0x0334 NV_30 "GeForce FX 5900ZT" +0x10de 0x0338 NV_30 "Quadro FX 3000" +0x10de 0x033f NV_30 "Quadro FX 700" +0x10de 0x0341 NV_30 "GeForce FX 5700 Ultra" +0x10de 0x0342 NV_30 "GeForce FX 5700" +0x10de 0x0343 NV_30 "GeForce FX 5700LE" +0x10de 0x0344 NV_30 "GeForce FX 5700VE" +0x10de 0x0345 NV_30 "NV36" +0x10de 0x034e NV_30 "Quadro FX 1100" +0x10de 0x034f NV_30 "NV36GL" +0x10de 0x0040 NV_40 "GeForce 6800 Ultra" +0x10de 0x0041 NV_40 "GeForce 6800" +0x10de 0x0042 NV_40 "GeForce 6800 LE" +0x10de 0x0043 NV_40 "NV40" +0x10de 0x0045 NV_40 "GeForce 6800 GT" +0x10de 0x0049 NV_40 "NV40GL" +0x10de 0x004e NV_30 "Quadro FX 4000" +0x10de 0x00c0 NV_40 "NV41" +0x10de 0x00c1 NV_40 "GeForce 6800" +0x10de 0x00c2 NV_40 "GeForce 6800 LE" +0x10de 0x00cc NV_30 "Quadro FX Go1400" +0x10de 0x00cd NV_30 "Quadro FX 3450/4000 SDI" +0x10de 0x00ce NV_30 "Quadro FX 1400" +0x10de 0x0140 NV_40 "GeForce 6600 GT" +0x10de 0x0141 NV_40 "GeForce 6600" +0x10de 0x0142 NV_40 "NV43" +0x10de 0x0143 NV_40 "NV43" +0x10de 0x0145 NV_40 "GeForce 6610 XL" +0x10de 0x014b NV_40 "NV43" +0x10de 0x014c NV_40 "NV43GL" +0x10de 0x014d NV_40 "NV43GL" +0x10de 0x014e NV_30 "Quadro FX 540" +0x10de 0x014f NV_40 "GeForce 6200" +0x10de 0x0160 NV_40 "NV44" +0x10de 0x0161 NV_40 "GeForce 6200 TurboCache(TM)" +0x10de 0x0162 NV_40 "NV44" +0x10de 0x0163 NV_40 "NV44" +0x10de 0x0165 NV_10 "Quadro NVS 285" +0x10de 0x016e NV_40 "NV44GL" +0x10de 0x0220 NV_40 "NV44" +0x10de 0x0221 NV_40 "NV44" +0x10de 0x0222 NV_40 "NV44" +0x10de 0x0211 NV_40 "GeForce 6800" +0x10de 0x0212 NV_40 "GeForce 6800 LE" +0x10de 0x0215 NV_40 "GeForce 6800 GT" +0x10de 0x00f0 NV_40 "GeForce 6800 Ultra" +0x10de 0x00f0 NV_40 "GeForce 6800" +0x10de 0x00f1 NV_40 "GeForce 6600 GT" +0x10de 0x00f1 NV_40 "GeForce 6600 GT" +0x10de 0x00f2 NV_40 "GeForce 6600" +0x10de 0x00f2 NV_40 "GeForce 6600" +0x10de 0x00f3 NV_40 "GeForce 6200" +0x10de 0x00f3 NV_40 "GeForce 6200" +0x10de 0x00f8 NV_30 "Quadro FX 4400" +0x10de 0x00f8 NV_30 "Quadro FX 3400" +0x10de 0x00f8 NV_30 "Quadro FX 3400/4400" +0x10de 0x00f9 NV_40 "GeForce 6800 Ultra" +0x10de 0x00f9 NV_40 "GeForce 6800 GT" +0x10de 0x00f9 NV_40 "GeForce 6800 Series GPU" +0x10de 0x0091 NV_10 "GeForce 7800 GTX" +0x10de 0x00fa NV_30 "GeForce PCX 5750" +0x10de 0x00fa NV_30 "GeForce PCX 5750" +0x10de 0x00fb NV_30 "GeForce PCX 5900" +0x10de 0x00fb NV_30 "GeForce PCX 5900" +0x10de 0x00fc NV_30 "GeForce PCX 5300" +0x10de 0x00fc NV_30 "Quadro FX 330" +0x10de 0x00fc NV_30 "GeForce PCX 5300" +0x10de 0x00fd NV_10 "Quadro NVS 280 PCI-E" +0x10de 0x00fd NV_30 "Quadro FX 330" +0x10de 0x00fd NV_10 "Quadro PCI-E Series" +0x10de 0x00fe NV_30 "Quadro FX 1300" +0x10de 0x00fe NV_30 "Quadro FX 1300" +0x10de 0x00ff NV_10 "GeForce PCX 4300" +0x10de 0x00ff NV_10 "GeForce PCX 4300" +0x10de 0x0112 NV_10 "GeForce2 Go" +0x10de 0x0174 NV_20 "GeForce4 440 Go" +0x10de 0x0175 NV_20 "GeForce4 420 Go" +0x10de 0x0176 NV_20 "GeForce4 420 Go 32M" +0x10de 0x0177 NV_20 "GeForce4 460 Go" +0x10de 0x0179 NV_20 "GeForce4 440 Go 64M" +0x10de 0x017d NV_20 "GeForce4 410 Go 16M" +0x10de 0x017c NV_20 "Quadro4 500 GoGL" +0x10de 0x0186 NV_20 "GeForce4 448 Go" +0x10de 0x0187 NV_20 "GeForce4 488 Go" +0x10de 0x018d NV_20 "GeForce4 448 Go" +0x10de 0x0286 NV_20 "GeForce4 4200 Go" +0x10de 0x028c NV_20 "Quadro4 700 GoGL" +0x10de 0x0316 NV_30 "NV31M" +0x10de 0x0317 NV_30 "NV31M Pro" +0x10de 0x031a NV_30 "GeForce FX Go5600" +0x10de 0x031b NV_30 "GeForce FX Go5650" +0x10de 0x031c NV_30 "Quadro FX Go700" +0x10de 0x031d NV_30 "NV31GLM" +0x10de 0x031e NV_30 "NV31GLM Pro" +0x10de 0x031f NV_30 "NV31GLM Pro" +0x10de 0x0324 NV_30 "GeForce FX Go5200" +0x10de 0x0325 NV_30 "GeForce FX Go5250" +0x10de 0x0328 NV_30 "GeForce FX Go5200 32M/64M" +0x10de 0x0329 NV_30 "NV34MAP" +0x10de 0x032c NV_30 "GeForce FX Go53xx" +0x10de 0x032d NV_30 "GeForce FX Go5100" +0x10de 0x0347 NV_30 "GeForce FX Go5700" +0x10de 0x0348 NV_30 "GeForce FX Go5700" +0x10de 0x0349 NV_30 "NV36M Pro" +0x10de 0x034b NV_30 "NV36MAP" +0x10de 0x034c NV_30 "Quadro FX Go1000" +0x10de 0x00c8 NV_30 "GeForce Go 6800" +0x10de 0x00c9 NV_30 "GeForce Go 6800 Ultra" +0x10de 0x00cc NV_30 "Quadro FX Go1400" +0x10de 0x0140 NV_40 "NV43" +0x10de 0x0144 NV_30 "GeForce Go 6600" +0x10de 0x0147 NV_40 "NV43" +0x10de 0x0148 NV_30 "GeForce Go 6600" +0x10de 0x0149 NV_40 "NV43" +0x10de 0x014c NV_40 "NV43GL" +0x10de 0x0164 NV_30 "GeForce Go 6200" +0x10de 0x0167 NV_30 "GeForce Go 6200" +0x10de 0x0169 NV_40 "NV44M" +0x10de 0x016b NV_40 "NV44GLM" +0x10de 0x016c NV_40 "NV44GLM" +0x10de 0x016d NV_40 "NV44GLM" +0x10de 0x0228 NV_40 "NV44M" +0x10de 0x0091 NV_10 "NVIDIA GeForce 7800 GTX" +0x10de 0x0092 NV_10 "NVIDIA GeForce 7800 GT" +0x10de 0x009d NV_30 "NVIDIA Quadro FX 4500" +0x10de 0x0240 NV_40 "NVIDIA GeForce 6150" +0x10de 0x0241 NV_40 "NVIDIA GeForce 6150 LE" +0x10de 0x0242 NV_40 "NVIDIA GeForce 6100" |
From: <dar...@ke...> - 2006-08-30 06:55:24
|
shared-core/nouveau_drm.h | 14 ++++++++++++++ shared-core/nouveau_drv.h | 2 ++ shared-core/nouveau_fifo.c | 2 ++ shared-core/nouveau_state.c | 36 ++++++++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+) New commits: diff-tree 24dddc27549f2b8cf837305ee84dd1ca97df98e7 (from 3cfab681b3c82c7951f1cc337d2021a6f0d08b1e) Author: Ben Skeggs <dar...@ii...> Date: Wed Aug 30 16:55:02 2006 +1000 Add stub {get,set}param ioctls. diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index eab8ca2..76fb3a1 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -79,6 +79,18 @@ typedef struct drm_nouveau_mem_free { } drm_nouveau_mem_free_t; +typedef struct drm_nouveau_getparam { + unsigned int param; + unsigned int value; +} +drm_nouveau_getparam_t; + +typedef struct drm_nouveau_setparam { + unsigned int param; + unsigned int value; +} +drm_nouveau_setparam_t; + enum nouveau_card_type { NV_UNKNOWN =0, NV_01 =1, @@ -114,6 +126,8 @@ drm_nouveau_sarea_t; #define DRM_NOUVEAU_DMA_OBJECT_INIT 0x03 // We don't want this eventually.. #define DRM_NOUVEAU_MEM_ALLOC 0x04 #define DRM_NOUVEAU_MEM_FREE 0x05 +#define DRM_NOUVEAU_GETPARAM 0x06 +#define DRM_NOUVEAU_SETPARAM 0x07 #endif /* __NOUVEAU_DRM_H__ */ diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index c4f9718..d701401 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -131,6 +131,8 @@ extern void nouveau_preclose(drm_device_ extern int nouveau_load(struct drm_device *dev, unsigned long flags); extern int nouveau_firstopen(struct drm_device *dev); extern int nouveau_unload(struct drm_device *dev); +extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS); +extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS); /* nouveau_mem.c */ extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 18ad7c5..c0d54b3 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -263,6 +263,8 @@ drm_ioctl_desc_t nouveau_ioctls[] = { [DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH}, + [DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH}, + [DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, }; int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 3bfa99c..01ebbc8 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -132,3 +132,39 @@ int nouveau_unload(struct drm_device *de return 0; } +int nouveau_ioctl_getparam(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_nouveau_getparam_t getparam; + + DRM_COPY_FROM_USER_IOCTL(getparam, (drm_nouveau_getparam_t __user *)data, + sizeof(getparam)); + + switch (getparam.param) { + default: + DRM_ERROR("unknown parameter %d\n", getparam.param); + return DRM_ERR(EINVAL); + } + + DRM_COPY_TO_USER_IOCTL((drm_nouveau_getparam_t __user *)data, getparam, + sizeof(getparam)); + return 0; +} + +int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) +{ + DRM_DEVICE; + drm_nouveau_setparam_t setparam; + + DRM_COPY_FROM_USER_IOCTL(setparam, (drm_nouveau_setparam_t __user *)data, + sizeof(setparam)); + + switch (setparam.param) { + default: + DRM_ERROR("unknown parameter %d\n", setparam.param); + return DRM_ERR(EINVAL); + } + + return 0; +} + |
From: <dar...@ke...> - 2006-09-02 12:26:09
|
shared-core/nouveau_object.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) New commits: diff-tree 97291a6ad05848b05af69e52453d93db1e96473b (from 24dddc27549f2b8cf837305ee84dd1ca97df98e7) Author: Ben Skeggs <dar...@ii...> Date: Sat Sep 2 22:25:26 2006 +1000 Use DMA_IN_MEMORY for DMA objects. This is needed for a DDX change that will be committed soon after this. Without the change, MEMFORMAT_DMA_OUT appears to have no effect. diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index fb30d52..f5c16c5 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -338,14 +338,17 @@ struct nouveau_object *nouveau_dma_objec | (adjust<<20) | (access<<14) | (target<<16) - | 2) + | 0x3D /* DMA_IN_MEMORY */) ); NV_WRITE(NV_RAMIN + obj->instance + 4, size - 1); NV_WRITE(NV_RAMIN + obj->instance + 8, frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0)); + /* I don't actually know what this is, the DMA objects I see + * in renouveau dumps usually have this as the same as +8 + */ NV_WRITE(NV_RAMIN + obj->instance + 12, - 0xFFFFFFFF); + frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0)); return obj; } |
From: <dar...@ke...> - 2006-09-02 20:36:41
|
shared-core/nouveau_drm.h | 2 shared-core/nouveau_drv.h | 13 ++++-- shared-core/nouveau_fifo.c | 16 ++++++- shared-core/nouveau_state.c | 89 +++++++++++++++++++++++++++++++------------- 4 files changed, 88 insertions(+), 32 deletions(-) New commits: diff-tree b119966ae65c9ee74096cf0b246bf7703cb58ec4 (from 97291a6ad05848b05af69e52453d93db1e96473b) Author: Ben Skeggs <dar...@ii...> Date: Sun Sep 3 06:36:06 2006 +1000 Allow cmdbuf location(AGP,VRAM) and size to be configured. diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 76fb3a1..1180a13 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -85,6 +85,8 @@ typedef struct drm_nouveau_getparam { } drm_nouveau_getparam_t; +#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1 +#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2 typedef struct drm_nouveau_setparam { unsigned int param; unsigned int value; diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index d701401..7af9c61 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -97,6 +97,13 @@ struct mem_block { drm_local_map_t *map; }; +struct nouveau_config { + struct { + int location; + int size; + } cmdbuf; +}; + typedef struct drm_nouveau_private { /* the card type, takes NV_* as values */ int card_type; @@ -111,9 +118,7 @@ typedef struct drm_nouveau_private { struct nouveau_object *fb_obj; struct nouveau_object *cmdbuf_obj; - int cmdbuf_location; - int cmdbuf_base; - int cmdbuf_ch_size; + int cmdbuf_ch_size; struct mem_block* cmdbuf_alloc; struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER]; @@ -123,6 +128,7 @@ typedef struct drm_nouveau_private { struct mem_block *fb_heap; struct mem_block *fb_nomap_heap; + struct nouveau_config config; } drm_nouveau_private_t; @@ -133,6 +139,7 @@ extern int nouveau_firstopen(struct drm_ extern int nouveau_unload(struct drm_device *dev); extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS); extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS); +extern int nouveau_dma_init(struct drm_device *dev); /* nouveau_mem.c */ extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index c0d54b3..67ee6c7 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -77,6 +77,15 @@ static int nouveau_fifo_init(drm_device_ int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; + /* Init cmdbuf on first FIFO init, this is delayed until now to + * give the ddx a chance to configure the cmdbuf with SETPARAM + */ + if (!dev_priv->cmdbuf_alloc) { + ret = nouveau_dma_init(dev); + if (ret) + return ret; + } + /* * Alright, here is the full story * Nvidia cards have multiple hw fifo contexts (praise them for that, @@ -120,7 +129,7 @@ static int nouveau_fifo_init(drm_device_ return ret; /* then, the fifo itself */ - init->cmdbuf = dev_priv->cmdbuf_base; + init->cmdbuf = dev_priv->cmdbuf_alloc->start; init->cmdbuf += init->channel * dev_priv->cmdbuf_ch_size; init->cmdbuf_size = dev_priv->cmdbuf_ch_size; ret = drm_addmap(dev, init->cmdbuf, init->cmdbuf_size, _DRM_REGISTERS, @@ -157,8 +166,9 @@ void nouveau_fifo_cleanup(drm_device_t * DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i); dev_priv->cur_fifo = i; } - - nouveau_pfifo_init(dev); + + if (dev_priv->cmdbuf_alloc) + nouveau_pfifo_init(dev); // nouveau_fifo_enable(dev); } diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 01ebbc8..fbe9464 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -76,32 +76,6 @@ int nouveau_firstopen(struct drm_device 0, nouveau_mem_fb_amount(dev), NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); - /* allocate one buffer for all the fifos */ - dev_priv->cmdbuf_alloc = nouveau_mem_alloc(dev, 0, 1024*1024, NOUVEAU_MEM_FB, (DRMFILE)-2); - - if (dev_priv->cmdbuf_alloc->flags&NOUVEAU_MEM_AGP) { - dev_priv->cmdbuf_location = NV_DMA_TARGET_AGP; - dev_priv->cmdbuf_ch_size = NV03_FIFO_SIZE; - dev_priv->cmdbuf_base = dev_priv->cmdbuf_alloc->start; - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - dev_priv->cmdbuf_base, nouveau_fifo_number(dev)*NV03_FIFO_SIZE, - NV_DMA_ACCESS_RO, dev_priv->cmdbuf_location); - } else { /* NOUVEAU_MEM_FB */ - dev_priv->cmdbuf_location = NV_DMA_TARGET_VIDMEM; - dev_priv->cmdbuf_ch_size = NV03_FIFO_SIZE; - dev_priv->cmdbuf_base = dev_priv->cmdbuf_alloc->start; - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - dev_priv->cmdbuf_base - drm_get_resource_start(dev, 1), - nouveau_fifo_number(dev)*NV03_FIFO_SIZE, - NV_DMA_ACCESS_RO, dev_priv->cmdbuf_location); - } - - DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", - (nouveau_fifo_number(dev)*dev_priv->cmdbuf_ch_size)/1024, - dev_priv->cmdbuf_base, - dev_priv->cmdbuf_location == NV_DMA_TARGET_AGP ? "AGP" : "VRAM" - ); - return 0; } @@ -154,12 +128,27 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARG int nouveau_ioctl_setparam(DRM_IOCTL_ARGS) { DRM_DEVICE; + drm_nouveau_private_t *dev_priv = dev->dev_private; drm_nouveau_setparam_t setparam; DRM_COPY_FROM_USER_IOCTL(setparam, (drm_nouveau_setparam_t __user *)data, sizeof(setparam)); switch (setparam.param) { + case NOUVEAU_SETPARAM_CMDBUF_LOCATION: + switch (setparam.value) { + case NOUVEAU_MEM_AGP: + case NOUVEAU_MEM_FB: + break; + default: + DRM_ERROR("invalid CMDBUF_LOCATION value=%d\n", setparam.value); + return DRM_ERR(EINVAL); + } + dev_priv->config.cmdbuf.location = setparam.value; + break; + case NOUVEAU_SETPARAM_CMDBUF_SIZE: + dev_priv->config.cmdbuf.size = setparam.value; + break; default: DRM_ERROR("unknown parameter %d\n", setparam.param); return DRM_ERR(EINVAL); @@ -168,3 +157,51 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARG return 0; } +int nouveau_dma_init(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_config *config = &dev_priv->config; + struct mem_block *cb; + int cb_min_size = nouveau_fifo_number(dev) * NV03_FIFO_SIZE; + + /* allocate one buffer for all the fifos */ + dev_priv->cmdbuf_alloc = nouveau_mem_alloc(dev, 0, 1024*1024, NOUVEAU_MEM_FB, (DRMFILE)-2); + + /* Defaults for unconfigured values */ + if (!config->cmdbuf.location) + config->cmdbuf.location = NOUVEAU_MEM_FB; + if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size) + config->cmdbuf.size = cb_min_size; + + cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, + config->cmdbuf.location, (DRMFILE)-2); + /* Try defaults if that didn't succeed */ + if (!cb) { + config->cmdbuf.location = NOUVEAU_MEM_FB; + config->cmdbuf.size = cb_min_size; + cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, + config->cmdbuf.location, (DRMFILE)-2); + } + if (!cb) { + DRM_ERROR("Couldn't allocate DMA command buffer.\n"); + return DRM_ERR(ENOMEM); + } + + if (config->cmdbuf.location == NOUVEAU_MEM_AGP) + dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, + cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP); + else + dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, + cb->start - drm_get_resource_start(dev, 1), + cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); + dev_priv->cmdbuf_ch_size = cb->size / nouveau_fifo_number(dev); + dev_priv->cmdbuf_alloc = cb; + + DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", + (uint32_t)cb->size>>10, (uint32_t)cb->start, + config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP"); + DRM_INFO("FIFO size is %dKiB\n", dev_priv->cmdbuf_ch_size>>10); + + return 0; +} + |
From: <ma...@ke...> - 2006-09-06 22:31:52
|
shared-core/nouveau_state.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) New commits: diff-tree d89c623f8e739815ea952adc77cfe5c0f7204407 (from b119966ae65c9ee74096cf0b246bf7703cb58ec4) Author: Stephane Marchesin <mar...@ic...> Date: Thu Sep 7 00:35:17 2006 +0200 Remove a 64 bit div. diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index fbe9464..707d42e 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -194,7 +194,7 @@ int nouveau_dma_init(struct drm_device * dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, cb->start - drm_get_resource_start(dev, 1), cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); - dev_priv->cmdbuf_ch_size = cb->size / nouveau_fifo_number(dev); + dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev); dev_priv->cmdbuf_alloc = cb; DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", |
From: <dar...@ke...> - 2006-09-07 13:59:35
|
shared-core/nouveau_fifo.c | 7 +++++++ shared-core/nouveau_object.c | 10 +--------- shared-core/nouveau_state.c | 15 ++++++--------- 3 files changed, 14 insertions(+), 18 deletions(-) New commits: diff-tree 0ef29768ca909421539c3d8f65bb8e94912fa597 (from d89c623f8e739815ea952adc77cfe5c0f7204407) Author: Ben Skeggs <dar...@ii...> Date: Thu Sep 7 23:59:19 2006 +1000 Fix second start of X server without module reload beforehand, and a couple of other fixes. - Mark the correct RAMIN slots as free (oops) - Remove a VRAM alloc that shouldn't have been there (oops) - Move HT init out of firstopen() and into dma_init() - Setup PFIFO_RAM{HT,FC,RO} in pfifo_init() diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 67ee6c7..ca7ddef 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -216,6 +216,13 @@ static void nouveau_pfifo_init(drm_devic NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000); NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); + NV_WRITE(NV_PFIFO_RAMHT, + (0x03 << 24) /* search 128 */ | + ((dev_priv->objs.ht_bits - 9) << 16) | + (dev_priv->objs.ht_base >> 8) + ); + NV_WRITE(NV_PFIFO_RAMFC, 0x00000110); /* RAMIN+0x11000 0.5k */ + NV_WRITE(NV_PFIFO_RAMRO, 0x00000112); /* RAMIN+0x11200 0.5k */ NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index f5c16c5..a7fe06c 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -241,7 +241,7 @@ static void nouveau_object_instance_free obj->instance >>= (dev_priv->card_type >=NV_40 ? 5 : 4); be = obj->instance / 32; bb = obj->instance % 32; - objs->inst_bmap[be] &= ~bb; + objs->inst_bmap[be] &= ~(1<<bb); objs->free_instance++; } @@ -265,14 +265,6 @@ void nouveau_hash_table_init(drm_device_ dev_priv->objs.ht_base = 0x10000; dev_priv->objs.ht_size = (1 << dev_priv->objs.ht_bits); - NV_WRITE(NV_PFIFO_RAMHT, - (0x03 << 24) /* search 128 */ | - ((dev_priv->objs.ht_bits - 9) << 16) | - ((dev_priv->objs.ht_base >> 16) << 4) - ); - NV_WRITE(NV_PFIFO_RAMFC, 0x00000110); /* RAMIN+0x11000 0.5k */ - NV_WRITE(NV_PFIFO_RAMRO, 0x00000112); /* RAMIN+0x11200 0.5k */ - dev_priv->objs.first_instance = 0x12000; dev_priv->objs.free_instance = 1024; /*FIXME*/ dev_priv->objs.num_instance = 1024; /*FIXME*/ diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 707d42e..6c5cc15 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -69,13 +69,6 @@ int nouveau_firstopen(struct drm_device else dev_priv->fb_usable_size=nouveau_mem_fb_amount(dev)-256*1024; - nouveau_hash_table_init(dev); - - if (dev_priv->card_type >= NV_40) - dev_priv->fb_obj = nouveau_dma_object_create(dev, - 0, nouveau_mem_fb_amount(dev), - NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); - return 0; } @@ -164,8 +157,12 @@ int nouveau_dma_init(struct drm_device * struct mem_block *cb; int cb_min_size = nouveau_fifo_number(dev) * NV03_FIFO_SIZE; - /* allocate one buffer for all the fifos */ - dev_priv->cmdbuf_alloc = nouveau_mem_alloc(dev, 0, 1024*1024, NOUVEAU_MEM_FB, (DRMFILE)-2); + nouveau_hash_table_init(dev); + + if (dev_priv->card_type >= NV_40) + dev_priv->fb_obj = nouveau_dma_object_create(dev, + 0, nouveau_mem_fb_amount(dev), + NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); /* Defaults for unconfigured values */ if (!config->cmdbuf.location) |
From: <dar...@ke...> - 2006-09-08 21:36:04
|
shared-core/nouveau_irq.c | 32 ++++++++++++++++++++++++++++++++ shared-core/nouveau_object.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) New commits: diff-tree aa80e2f48f291aa41524dfb53023499c91473705 (from 0ef29768ca909421539c3d8f65bb8e94912fa597) Author: Ben Skeggs <dar...@ii...> Date: Sat Sep 9 07:35:55 2006 +1000 Add copyright notices while I still remember.. diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index d469129..5088eda 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -1,3 +1,35 @@ +/* + * Copyright (C) 2006 Ben Skeggs. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * Authors: + * Ben Skeggs <dar...@ii...> + */ + #include "drmP.h" #include "drm.h" #include "nouveau_drm.h" diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index a7fe06c..4e0571b 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -1,3 +1,35 @@ +/* + * Copyright (C) 2006 Ben Skeggs. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * Authors: + * Ben Skeggs <dar...@ii...> + */ + #include "drmP.h" #include "drm.h" #include "nouveau_drv.h" |
From: <dar...@ke...> - 2006-09-16 17:01:02
|
shared-core/drm_pciids.txt | 1 + 1 files changed, 1 insertion(+) New commits: diff-tree 22382bd8c540231641bfc75d778a50ddf1463783 (from aa80e2f48f291aa41524dfb53023499c91473705) Author: Ben Skeggs <dar...@ii...> Date: Sun Sep 17 13:00:27 2006 +1000 Add pciid for GeForce Go 6150 (0x0244). diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 9f42195..cbb30d2 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -669,3 +669,4 @@ 0x10de 0x0240 NV_40 "NVIDIA GeForce 6150" 0x10de 0x0241 NV_40 "NVIDIA GeForce 6150 LE" 0x10de 0x0242 NV_40 "NVIDIA GeForce 6100" +0x10de 0x0244 NV_40 "NVIDIA GeForce 6150 Go" |
From: <ma...@ke...> - 2006-10-10 22:25:28
|
shared-core/nouveau_drm.h | 19 +- shared-core/nouveau_drv.h | 5 shared-core/nouveau_fifo.c | 308 ++++++++++++++++++++++++++++---------------- shared-core/nouveau_irq.c | 122 ++++++++++++++++- shared-core/nouveau_reg.h | 83 +++++++++++ shared-core/nouveau_state.c | 59 +------- 6 files changed, 412 insertions(+), 184 deletions(-) New commits: diff-tree dd473411f889cc16af255437d2a61c616bcee695 (from 22382bd8c540231641bfc75d778a50ddf1463783) Author: Stephane Marchesin <mar...@ic...> Date: Wed Oct 11 00:28:15 2006 +0200 Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX. diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 1180a13..ed87f5c 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -25,7 +25,7 @@ #ifndef __NOUVEAU_DRM_H__ #define __NOUVEAU_DRM_H__ -typedef struct drm_nouveau_fifo_init { +typedef struct drm_nouveau_fifo_alloc { int channel; uint32_t put_base; /* FIFO control regs */ @@ -35,7 +35,7 @@ typedef struct drm_nouveau_fifo_init { drm_handle_t cmdbuf; int cmdbuf_size; } -drm_nouveau_fifo_init_t; +drm_nouveau_fifo_alloc_t; typedef struct drm_nouveau_object_init { uint32_t handle; @@ -122,14 +122,13 @@ typedef struct drm_nouveau_sarea { } drm_nouveau_sarea_t; -#define DRM_NOUVEAU_FIFO_INIT 0x00 -#define DRM_NOUVEAU_PFIFO_REINIT 0x01 -#define DRM_NOUVEAU_OBJECT_INIT 0x02 -#define DRM_NOUVEAU_DMA_OBJECT_INIT 0x03 // We don't want this eventually.. -#define DRM_NOUVEAU_MEM_ALLOC 0x04 -#define DRM_NOUVEAU_MEM_FREE 0x05 -#define DRM_NOUVEAU_GETPARAM 0x06 -#define DRM_NOUVEAU_SETPARAM 0x07 +#define DRM_NOUVEAU_FIFO_ALLOC 0x00 +#define DRM_NOUVEAU_OBJECT_INIT 0x01 +#define DRM_NOUVEAU_DMA_OBJECT_INIT 0x02 // We don't want this eventually.. +#define DRM_NOUVEAU_MEM_ALLOC 0x03 +#define DRM_NOUVEAU_MEM_FREE 0x04 +#define DRM_NOUVEAU_GETPARAM 0x05 +#define DRM_NOUVEAU_SETPARAM 0x06 #endif /* __NOUVEAU_DRM_H__ */ diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 7af9c61..007bdd6 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -123,6 +123,9 @@ typedef struct drm_nouveau_private { struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER]; struct nouveau_object_store objs; + /* RAMFC and RAMRO offsets */ + uint32_t ramfc_offset; + uint32_t ramro_offset; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -139,7 +142,7 @@ extern int nouveau_firstopen(struct drm_ extern int nouveau_unload(struct drm_device *dev); extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS); extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS); -extern int nouveau_dma_init(struct drm_device *dev); +extern void nouveau_wait_for_idle(struct drm_device *dev); /* nouveau_mem.c */ extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev); diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index ca7ddef..de23f96 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -44,23 +44,6 @@ int nouveau_fifo_number(drm_device_t* de } } -/* setup the fifo enable register */ -static void nouveau_fifo_enable(drm_device_t* dev) -{ - int i; - unsigned enable_val=0; - drm_nouveau_private_t *dev_priv = dev->dev_private; - - for(i=31;i>=0;i--) - { - enable_val<<=1; - if (dev_priv->fifos[i].used) - enable_val|=1; - } - DRM_DEBUG("enable_val=0x%08x\n", enable_val); - NV_WRITE(NV03_FIFO_ENABLE,enable_val); -} - /*********************************** * functions doing the actual work ***********************************/ @@ -70,12 +53,141 @@ static void nouveau_fifo_enable(drm_devi * voir nv_driver.c : NVPreInit */ -/* initializes a fifo */ -static int nouveau_fifo_init(drm_device_t* dev,drm_nouveau_fifo_init_t* init, DRMFILE filp) +static void nouveau_fifo_init(drm_device_t* dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + + /* Init PFIFO - This is an exact copy of what's done in the Xorg ddx so far. + * We should be able to figure out what's happening from the + * resources available.. + */ + + if (dev->irq_enabled) + nouveau_irq_postinstall(dev); + + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4); + + DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo); + + NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + NV_WRITE(NV_PFIFO_MODE, 0x00000000); + + NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo); + else + NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo); + NV_WRITE(NV_PFIFO_CACH1_DMAP, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); + NV_WRITE(NV_PFIFO_CACH1_DMAG, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); + NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); + NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000); + NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000); + NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); + NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); + NV_WRITE(NV_PFIFO_RAMHT, + (0x03 << 24) /* search 128 */ | + ((dev_priv->objs.ht_bits - 9) << 16) | + (dev_priv->objs.ht_base >> 8) + ); + dev_priv->ramfc_offset=0x11000; + dev_priv->ramro_offset=0x11200; + NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ + NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */ + NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000); + NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); +#ifdef __BIG_ENDIAN + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); + NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); + + NV_WRITE(NV_PGRAPH_CTX_USER, 0x0); + NV_WRITE(NV_PGRAPH_CTX_SWITCH1, 0x19); + NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ ); + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001); + else + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000); + + NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff); + NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + + DRM_DEBUG("%s: CACHE1 GET/PUT readback %d/%d\n", __func__, + NV_READ(NV_PFIFO_CACH1_DMAG), + NV_READ(NV_PFIFO_CACH1_DMAP)); + + DRM_INFO("%s: OK\n", __func__); +} + +static int nouveau_dma_init(struct drm_device *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + struct nouveau_config *config = &dev_priv->config; + struct mem_block *cb; + int cb_min_size = nouveau_fifo_number(dev) * NV03_FIFO_SIZE; + + /* XXX this should be done earlier on init */ + nouveau_hash_table_init(dev); + + if (dev_priv->card_type >= NV_40) + dev_priv->fb_obj = nouveau_dma_object_create(dev, + 0, nouveau_mem_fb_amount(dev), + NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); + + /* Defaults for unconfigured values */ + if (!config->cmdbuf.location) + config->cmdbuf.location = NOUVEAU_MEM_FB; + if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size) + config->cmdbuf.size = cb_min_size; + + cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, + config->cmdbuf.location, (DRMFILE)-2); + /* Try defaults if that didn't succeed */ + if (!cb) { + config->cmdbuf.location = NOUVEAU_MEM_FB; + config->cmdbuf.size = cb_min_size; + cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, + config->cmdbuf.location, (DRMFILE)-2); + } + if (!cb) { + DRM_ERROR("Couldn't allocate DMA command buffer.\n"); + return DRM_ERR(ENOMEM); + } + + if (config->cmdbuf.location == NOUVEAU_MEM_AGP) + dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, + cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP); + else + dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, + cb->start - drm_get_resource_start(dev, 1), + cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); + dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev); + dev_priv->cmdbuf_alloc = cb; + + nouveau_fifo_init(dev); + DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", + (uint32_t)cb->size>>10, (uint32_t)cb->start, + config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP"); + DRM_INFO("FIFO size is %dKiB\n", dev_priv->cmdbuf_ch_size>>10); + + return 0; +} + +/* allocates and initializes a fifo for user space consumption */ +static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp) { int i; int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t ctx_addr; /* Init cmdbuf on first FIFO init, this is delayed until now to * give the ddx a chance to configure the cmdbuf with SETPARAM @@ -90,18 +202,15 @@ static int nouveau_fifo_init(drm_device_ * Alright, here is the full story * Nvidia cards have multiple hw fifo contexts (praise them for that, * no complicated crash-prone context switches) - * X always uses context 0 (0x00800000) * We allocate a new context for each app and let it write to it directly * (woo, full userspace command submission !) * When there are no more contexts, you lost */ for(i=0;i<nouveau_fifo_number(dev);i++) if (dev_priv->fifos[i].used==0) - { - dev_priv->fifos[i].used=1; break; - } + DRM_INFO("Allocating FIFO number %d\n", i); /* no more fifos. you lost. */ if (i==nouveau_fifo_number(dev)) return DRM_ERR(EINVAL); @@ -110,16 +219,49 @@ static int nouveau_fifo_init(drm_device_ dev_priv->fifos[i].used=1; dev_priv->fifos[i].filp=filp; - /* enable the fifo */ - nouveau_fifo_enable(dev); + nouveau_wait_for_idle(dev); + + /* disable the fifo caches */ + NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + + // FIXME i*32 is true on nv04, what is it on >=nv10 ? + ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+i*32; + + // clear the first 2 RAMFC entries + // FIXME try to fill GET/PUT and see what that changes + NV_WRITE(ctx_addr,0x0); + NV_WRITE(ctx_addr+4,0x0); + + // FIXME that's what is done in nvosdk, but that part of the code is buggy so... + // RAMFC + 8 = instoffset + NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); + + // RAMFC + 16 = defaultFetch + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + + /* enable the fifo dma operation */ + NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<i)); + + // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); + + dev_priv->cur_fifo=i; + if (dev_priv->card_type >= NV_40) + NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo); + else + NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo); - /* make the fifo available to user space */ init->channel = i; init->put_base = i*dev_priv->cmdbuf_ch_size; NV_WRITE(NV03_FIFO_REGS_DMAPUT(i), init->put_base); NV_WRITE(NV03_FIFO_REGS_DMAGET(i), init->put_base); + NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); + NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); + /* reenable the fifo caches */ + NV_WRITE(NV_PFIFO_CACHES, 0x00000001); + + /* make the fifo available to user space */ /* first, the fifo control regs */ init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(i); init->ctrl_size = NV03_FIFO_REGS_SIZE; @@ -140,14 +282,29 @@ static int nouveau_fifo_init(drm_device_ /* FIFO has no objects yet */ dev_priv->fifos[i].objs = NULL; - DRM_DEBUG("%s: initialised FIFO %d\n", __func__, i); - dev_priv->cur_fifo = i; + DRM_INFO("%s: initialised FIFO %d\n", __func__, i); return 0; } -static void nouveau_pfifo_init(drm_device_t* dev); + +/* stops a fifo */ +void nouveau_fifo_free(drm_device_t* dev,int n) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + dev_priv->fifos[n].used=0; + DRM_DEBUG("%s: freeing fifo %d\n", __func__, n); + + /* disable the fifo caches */ + NV_WRITE(NV_PFIFO_CACHES, 0x00000000); + + NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n)); + // FIXME XXX needs more code + + /* reenable the fifo caches */ + NV_WRITE(NV_PFIFO_CACHES, 0x00000001); +} /* cleanups all the fifos from filp */ -void nouveau_fifo_cleanup(drm_device_t * dev, DRMFILE filp) +void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp) { int i; drm_nouveau_private_t *dev_priv = dev->dev_private; @@ -155,9 +312,10 @@ void nouveau_fifo_cleanup(drm_device_t * DRM_DEBUG("clearing FIFO enables from filp\n"); for(i=0;i<nouveau_fifo_number(dev);i++) if (dev_priv->fifos[i].filp==filp) - dev_priv->fifos[i].used=0; + nouveau_fifo_free(dev,i); - if (dev_priv->cur_fifo == i) { + /* check we still point at an active channel */ + if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) { DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__); for (i=0;i<nouveau_fifo_number(dev);i++) if (dev_priv->fifos[i].used) break; @@ -167,9 +325,8 @@ void nouveau_fifo_cleanup(drm_device_t * dev_priv->cur_fifo = i; } - if (dev_priv->cmdbuf_alloc) - nouveau_pfifo_init(dev); -// nouveau_fifo_enable(dev); +/* if (dev_priv->cmdbuf_alloc) + nouveau_fifo_init(dev);*/ } int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp) @@ -183,99 +340,30 @@ int nouveau_fifo_id_get(drm_device_t* de return -1; } -static void nouveau_pfifo_init(drm_device_t* dev) -{ - drm_nouveau_private_t *dev_priv = dev->dev_private; - - /* Init PFIFO - This is an exact copy of what's done in the Xorg ddx so far. - * We should be able to figure out what's happening from the - * resources available.. - */ - - if (dev->irq_enabled) - nouveau_irq_postinstall(dev); - - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4); - - DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo); - - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - nouveau_fifo_enable(dev); - - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - if (dev_priv->card_type >= NV_40) - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo); - else - NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo); - NV_WRITE(NV_PFIFO_CACH1_DMAP, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); - NV_WRITE(NV_PFIFO_CACH1_DMAG, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size); - NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4); - NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); - NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); - NV_WRITE(NV_PFIFO_RAMHT, - (0x03 << 24) /* search 128 */ | - ((dev_priv->objs.ht_bits - 9) << 16) | - (dev_priv->objs.ht_base >> 8) - ); - NV_WRITE(NV_PFIFO_RAMFC, 0x00000110); /* RAMIN+0x11000 0.5k */ - NV_WRITE(NV_PFIFO_RAMRO, 0x00000112); /* RAMIN+0x11200 0.5k */ - NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000); -#ifdef __BIG_ENDIAN - NV_WRITE(NV_PFIFO_CACH1_DMAF, 0x800F0078); -#else - NV_WRITE(NV_PFIFO_CACH1_DMAF, 0x000F0078); -#endif - NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); - - DRM_DEBUG("%s: CACHE1 GET/PUT readback %d/%d\n", __func__, - NV_READ(NV_PFIFO_CACH1_DMAG), - NV_READ(NV_PFIFO_CACH1_DMAP)); -} - /*********************************** * ioctls wrapping the functions ***********************************/ -static int nouveau_ioctl_fifo_init(DRM_IOCTL_ARGS) +static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_nouveau_fifo_init_t init; + drm_nouveau_fifo_alloc_t init; int res; - DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_init_t __user *) data, sizeof(init)); + DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init)); - res=nouveau_fifo_init(dev,&init,filp); + res=nouveau_fifo_alloc(dev,&init,filp); if (!res) - DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_init_t __user *)data, init, sizeof(init)); + DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init)); return res; } -static int nouveau_ioctl_fifo_reinit(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - - nouveau_pfifo_init(dev); - return 0; -} - /*********************************** * finally, the ioctl table ***********************************/ drm_ioctl_desc_t nouveau_ioctls[] = { - [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_INIT)] = {nouveau_ioctl_fifo_init, DRM_AUTH}, - [DRM_IOCTL_NR(DRM_NOUVEAU_PFIFO_REINIT)] = {nouveau_ioctl_fifo_reinit, DRM_AUTH}, + [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH}, [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH}, diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 5088eda..9cd2c77 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -46,7 +46,10 @@ void nouveau_irq_preinstall(drm_device_t NV_WRITE(NV_PFIFO_INTEN, 0); NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF); /* Disable/Clear PGRAPH interrupts */ - NV_WRITE(NV_PGRAPH_INTEN, 0); + if (dev_priv->card_type<NV_40) + NV_WRITE(NV04_PGRAPH_INTEN, 0); + else + NV_WRITE(NV40_PGRAPH_INTEN, 0); NV_WRITE(NV_PGRAPH_INTSTAT, 0xFFFFFFFF); #if 0 /* Disable/Clear CRTC0/1 interrupts */ @@ -70,9 +73,19 @@ void nouveau_irq_postinstall(drm_device_ NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF); /* Enable PGRAPH interrupts */ - NV_WRITE(NV_PGRAPH_INTEN, + if (dev_priv->card_type<NV_40) + NV_WRITE(NV04_PGRAPH_INTEN, NV_PGRAPH_INTR_NOTIFY | NV_PGRAPH_INTR_MISSING_HW | + NV_PGRAPH_INTR_CONTEXT_SWITCH | + NV_PGRAPH_INTR_BUFFER_NOTIFY | + NV_PGRAPH_INTR_ERROR + ); + else + NV_WRITE(NV40_PGRAPH_INTEN, + NV_PGRAPH_INTR_NOTIFY | + NV_PGRAPH_INTR_MISSING_HW | + NV_PGRAPH_INTR_CONTEXT_SWITCH | NV_PGRAPH_INTR_BUFFER_NOTIFY | NV_PGRAPH_INTR_ERROR ); @@ -97,7 +110,10 @@ void nouveau_irq_uninstall(drm_device_t /* Disable PFIFO interrupts */ NV_WRITE(NV_PFIFO_INTEN, 0); /* Disable PGRAPH interrupts */ - NV_WRITE(NV_PGRAPH_INTEN, 0); + if (dev_priv->card_type<NV_40) + NV_WRITE(NV04_PGRAPH_INTEN, 0); + else + NV_WRITE(NV40_PGRAPH_INTEN, 0); #if 0 /* Disable CRTC0/1 interrupts */ NV_WRITE(NV_CRTC0_INTEN, 0); @@ -107,15 +123,16 @@ void nouveau_irq_uninstall(drm_device_t NV_WRITE(NV_PMC_INTEN, 0); } -void nouveau_fifo_irq_handler(drm_nouveau_private_t *dev_priv) +static void nouveau_fifo_irq_handler(drm_device_t *dev) { uint32_t status, chmode, chstat; + drm_nouveau_private_t *dev_priv = dev->dev_private; status = NV_READ(NV_PFIFO_INTSTAT); if (!status) return; chmode = NV_READ(NV_PFIFO_MODE); - chstat = NV_READ(0x2508); + chstat = NV_READ(NV_PFIFO_DMA); DRM_DEBUG("NV: PFIFO interrupt! INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", status, chmode, chstat); @@ -136,9 +153,73 @@ void nouveau_fifo_irq_handler(drm_nouvea NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PFIFO_PENDING); } -void nouveau_pgraph_irq_handler(drm_nouveau_private_t *dev_priv) +static void nouveau_nv04_context_switch(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t channel,i; + uint32_t max=0; + NV_WRITE(NV_PGRAPH_FIFO,0x0); + channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV_PFIFO_CACH1_PSH1)); + //DRM_INFO("currently on channel %d\n",channel); + for (i=0;i<nouveau_fifo_number(dev);i++) + if ((dev_priv->fifos[i].used)&&(i!=channel)) { + uint32_t put,get,pending; + //put=NV_READ(dev_priv->ramfc_offset+i*32); + //get=NV_READ(dev_priv->ramfc_offset+4+i*32); + put=NV_READ(NV03_FIFO_REGS_DMAPUT(i)); + get=NV_READ(NV03_FIFO_REGS_DMAGET(i)); + pending=NV_READ(NV_PFIFO_DMA); + //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get); + /* mark all pending channels as such */ + if ((put!=get)&!(pending&(1<<i))) + { + pending|=(1<<i); + NV_WRITE(NV_PFIFO_DMA,pending); + } + max++; + } + nouveau_wait_for_idle(dev); + +#if 1 + /* 2-channel commute */ + // NV_WRITE(NV_PFIFO_CACH1_PSH1,channel|0x100); + if (channel==0) + channel=1; + else + channel=0; + // dev_priv->cur_fifo=channel; + NV_WRITE(0x2050,channel|0x100); +#endif + //NV_WRITE(NV_PFIFO_CACH1_PSH1,max|0x100); + //NV_WRITE(0x2050,max|0x100); + + NV_WRITE(NV_PGRAPH_FIFO,0x1); + +} + +static void nouveau_nv10_context_switch(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + int channel; + + channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + /* 2-channel commute */ + if (channel==0) + channel=1; + else + channel=0; + dev_priv->cur_fifo=channel; + + NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER)&0xE0FFFFFF)|(dev_priv->cur_fifo<<24)); + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); +} + +static void nouveau_pgraph_irq_handler(drm_device_t *dev) { uint32_t status; + drm_nouveau_private_t *dev_priv = dev->dev_private; status = NV_READ(NV_PGRAPH_INTSTAT); if (!status) @@ -190,6 +271,26 @@ void nouveau_pgraph_irq_handler(drm_nouv NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_ERROR); } + if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { + uint32_t channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1); + DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel); + switch(dev_priv->card_type) + { + case NV_04: + nouveau_nv04_context_switch(dev); + break; + case NV_10: + nouveau_nv10_context_switch(dev); + break; + default: + DRM_INFO("NV: Context switch not implemented\n"); + break; + } + + status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_CONTEXT_SWITCH); + } + if (status) { DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status); NV_WRITE(NV_PGRAPH_INTSTAT, status); @@ -198,8 +299,9 @@ void nouveau_pgraph_irq_handler(drm_nouv NV_WRITE(NV_PMC_INTSTAT, NV_PMC_INTSTAT_PGRAPH_PENDING); } -void nouveau_crtc_irq_handler(drm_nouveau_private_t *dev_priv, int crtc) +static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc) { + drm_nouveau_private_t *dev_priv = dev->dev_private; if (crtc&1) { NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); } @@ -220,15 +322,15 @@ irqreturn_t nouveau_irq_handler(DRM_IRQ_ DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status); if (status & NV_PMC_INTSTAT_PFIFO_PENDING) { - nouveau_fifo_irq_handler(dev_priv); + nouveau_fifo_irq_handler(dev); status &= ~NV_PMC_INTSTAT_PFIFO_PENDING; } if (status & NV_PMC_INTSTAT_PGRAPH_PENDING) { - nouveau_pgraph_irq_handler(dev_priv); + nouveau_pgraph_irq_handler(dev); status &= ~NV_PMC_INTSTAT_PGRAPH_PENDING; } if (status & NV_PMC_INTSTAT_CRTCn_PENDING) { - nouveau_crtc_irq_handler(dev_priv, (status>>24)&3); + nouveau_crtc_irq_handler(dev, (status>>24)&3); status &= ~NV_PMC_INTSTAT_CRTCn_PENDING; } diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 42c5b85..2b723c7 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -15,8 +15,8 @@ # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 -#define NV03_STATUS 0x004006b0 -#define NV04_STATUS 0x00400700 +#define NV03_PGRAPH_STATUS 0x004006b0 +#define NV04_PGRAPH_STATUS 0x00400700 #define NV_RAMIN 0x00700000 @@ -55,16 +55,24 @@ # define NV_PMC_INTEN_MASTER_ENABLE (1<< 0) #define NV_PGRAPH_INTSTAT 0x00400100 -#define NV_PGRAPH_INTEN 0x00400140 +#define NV04_PGRAPH_INTEN 0x00400140 +#define NV40_PGRAPH_INTEN 0x0040013C # define NV_PGRAPH_INTR_NOTIFY (1<< 0) # define NV_PGRAPH_INTR_MISSING_HW (1<< 4) +# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) # define NV_PGRAPH_INTR_ERROR (1<<20) +#define NV_PGRAPH_CTX_CONTROL 0x00400144 #define NV_PGRAPH_NV40_UNK220 0x00400220 # define NV_PGRAPH_NV40_UNK220_FB_INSTANCE +#define NV_PGRAPH_CTX_USER 0x00400148 +#define NV_PGRAPH_CTX_SWITCH1 0x0040014C +#define NV_PGRAPH_FIFO 0x00400720 +#define NV_PGRAPH_FFINTFC_ST2 0x00400764 /* It's a guess that this works on NV03. Confirmed on NV04, though */ -#define NV03_FIFO_ENABLE 0x00002504 +#define NV_PFIFO_DELAY_0 0x00002040 +#define NV_PFIFO_DMA_TIMESLICE 0x00002044 #define NV_PFIFO_INTSTAT 0x00002100 #define NV_PFIFO_INTEN 0x00002140 # define NV_PFIFO_INTR_ERROR (1<<0) @@ -73,14 +81,78 @@ #define NV_PFIFO_RAMRO 0x00002218 #define NV_PFIFO_CACHES 0x00002500 #define NV_PFIFO_MODE 0x00002504 +#define NV_PFIFO_DMA 0x00002508 #define NV_PFIFO_SIZE 0x0000250c #define NV_PFIFO_CACH0_PSH0 0x00003000 #define NV_PFIFO_CACH0_PUL0 0x00003050 #define NV_PFIFO_CACH0_PUL1 0x00003054 #define NV_PFIFO_CACH1_PSH0 0x00003200 #define NV_PFIFO_CACH1_PSH1 0x00003204 -#define NV_PFIFO_CACH1_DMAS 0x00003220 +#define NV_PFIFO_CACH1_DMAPSH 0x00003220 #define NV_PFIFO_CACH1_DMAF 0x00003224 +# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 +# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 +# define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008 +# define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010 +# define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018 +# define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020 +# define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028 +# define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030 +# define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038 +# define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040 +# define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048 +# define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050 +# define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058 +# define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060 +# define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068 +# define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070 +# define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078 +# define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080 +# define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088 +# define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090 +# define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098 +# define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0 +# define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8 +# define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0 +# define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8 +# define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0 +# define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8 +# define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0 +# define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8 +# define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0 +# define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8 +# define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0 +# define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8 +# define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000 +# define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000 +# define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000 +# define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000 +# define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000 +# define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000 +# define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000 +# define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000 +# define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000 +# define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000 +# define NV_PFIFO_CACH1_ENDIAN 0x80000000 +# define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF +# define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000 +#define NV_PFIFO_CACH1_DMAS 0x00003228 #define NV_PFIFO_CACH1_DMAI 0x0000322c #define NV_PFIFO_CACH1_DMAC 0x00003230 #define NV_PFIFO_CACH1_DMAP 0x00003240 @@ -101,3 +173,4 @@ #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) + diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index 6c5cc15..a015a0f 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -150,55 +150,18 @@ int nouveau_ioctl_setparam(DRM_IOCTL_ARG return 0; } -int nouveau_dma_init(struct drm_device *dev) +/* waits for idle */ +void nouveau_wait_for_idle(struct drm_device *dev) { - drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_config *config = &dev_priv->config; - struct mem_block *cb; - int cb_min_size = nouveau_fifo_number(dev) * NV03_FIFO_SIZE; - - nouveau_hash_table_init(dev); - - if (dev_priv->card_type >= NV_40) - dev_priv->fb_obj = nouveau_dma_object_create(dev, - 0, nouveau_mem_fb_amount(dev), - NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM); - - /* Defaults for unconfigured values */ - if (!config->cmdbuf.location) - config->cmdbuf.location = NOUVEAU_MEM_FB; - if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size) - config->cmdbuf.size = cb_min_size; - - cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, - config->cmdbuf.location, (DRMFILE)-2); - /* Try defaults if that didn't succeed */ - if (!cb) { - config->cmdbuf.location = NOUVEAU_MEM_FB; - config->cmdbuf.size = cb_min_size; - cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size, - config->cmdbuf.location, (DRMFILE)-2); - } - if (!cb) { - DRM_ERROR("Couldn't allocate DMA command buffer.\n"); - return DRM_ERR(ENOMEM); + drm_nouveau_private_t *dev_priv=dev->dev_private; + switch(dev_priv->card_type) + { + case NV_03: + while(NV_READ(NV03_PGRAPH_STATUS)); + break; + default: + while(NV_READ(NV04_PGRAPH_STATUS)); + break; } - - if (config->cmdbuf.location == NOUVEAU_MEM_AGP) - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP); - else - dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev, - cb->start - drm_get_resource_start(dev, 1), - cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM); - dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev); - dev_priv->cmdbuf_alloc = cb; - - DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n", - (uint32_t)cb->size>>10, (uint32_t)cb->start, - config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP"); - DRM_INFO("FIFO size is %dKiB\n", dev_priv->cmdbuf_ch_size>>10); - - return 0; } |
From: <ma...@ke...> - 2006-10-11 23:02:35
|
shared-core/nouveau_fifo.c | 72 +++++++++++++++++++++++++++------------------ shared-core/nouveau_irq.c | 4 +- 2 files changed, 47 insertions(+), 29 deletions(-) New commits: diff-tree a749d9d5b49ea0e402848bd6024e5c44826e784f (from dd473411f889cc16af255437d2a61c616bcee695) Author: Stephane Marchesin <mar...@ic...> Date: Thu Oct 12 01:08:15 2006 +0200 More work on the context switch code. Still doesn't work. I'm mostly convinced it's an initialization issue. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index de23f96..da9a863 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -110,7 +110,6 @@ static void nouveau_fifo_init(drm_device NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); NV_WRITE(NV_PGRAPH_CTX_USER, 0x0); - NV_WRITE(NV_PGRAPH_CTX_SWITCH1, 0x19); NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ ); if (dev_priv->card_type >= NV_40) NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001); @@ -187,7 +186,7 @@ static int nouveau_fifo_alloc(drm_device int i; int ret; drm_nouveau_private_t *dev_priv = dev->dev_private; - uint32_t ctx_addr; + uint32_t ctx_addr,ctx_size; /* Init cmdbuf on first FIFO init, this is delayed until now to * give the ddx a chance to configure the cmdbuf with SETPARAM @@ -219,54 +218,71 @@ static int nouveau_fifo_alloc(drm_device dev_priv->fifos[i].used=1; dev_priv->fifos[i].filp=filp; + init->channel = i; + init->put_base = i*dev_priv->cmdbuf_ch_size; + dev_priv->cur_fifo = init->channel; + nouveau_wait_for_idle(dev); /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - // FIXME i*32 is true on nv04, what is it on >=nv10 ? - ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+i*32; - - // clear the first 2 RAMFC entries - // FIXME try to fill GET/PUT and see what that changes - NV_WRITE(ctx_addr,0x0); - NV_WRITE(ctx_addr+4,0x0); - - // FIXME that's what is done in nvosdk, but that part of the code is buggy so... - // RAMFC + 8 = instoffset - NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); + if (dev_priv->card_type <= NV_04) + ctx_size=32; + else + ctx_size=128; - // RAMFC + 16 = defaultFetch - NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); + ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; + // clear the fifo context + for(i=0;i<ctx_size/4;i++) + NV_WRITE(ctx_addr+4*i,0x0); + + NV_WRITE(ctx_addr,init->put_base); + NV_WRITE(ctx_addr+4,init->put_base); + if (dev_priv->card_type <= NV_04) + { + // that's what is done in nvosdk, but that part of the code is buggy so... + NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); +#ifdef __BIG_ENDIAN + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + } + else + { + NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/); +#ifdef __BIG_ENDIAN + NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); +#else + NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); +#endif + } /* enable the fifo dma operation */ - NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<i)); + NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); - dev_priv->cur_fifo=i; if (dev_priv->card_type >= NV_40) NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo); else NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo); - init->channel = i; - init->put_base = i*dev_priv->cmdbuf_ch_size; - - NV_WRITE(NV03_FIFO_REGS_DMAPUT(i), init->put_base); - NV_WRITE(NV03_FIFO_REGS_DMAGET(i), init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); + NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); + NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); /* reenable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000001); /* make the fifo available to user space */ /* first, the fifo control regs */ - init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(i); + init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel); init->ctrl_size = NV03_FIFO_REGS_SIZE; ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS, - 0, &dev_priv->fifos[i].regs); + 0, &dev_priv->fifos[init->channel].regs); if (ret != 0) return ret; @@ -275,14 +291,14 @@ static int nouveau_fifo_alloc(drm_device init->cmdbuf += init->channel * dev_priv->cmdbuf_ch_size; init->cmdbuf_size = dev_priv->cmdbuf_ch_size; ret = drm_addmap(dev, init->cmdbuf, init->cmdbuf_size, _DRM_REGISTERS, - 0, &dev_priv->fifos[i].map); + 0, &dev_priv->fifos[init->channel].map); if (ret != 0) return ret; /* FIFO has no objects yet */ - dev_priv->fifos[i].objs = NULL; + dev_priv->fifos[init->channel].objs = NULL; - DRM_INFO("%s: initialised FIFO %d\n", __func__, i); + DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel); return 0; } @@ -291,7 +307,7 @@ void nouveau_fifo_free(drm_device_t* dev { drm_nouveau_private_t *dev_priv = dev->dev_private; dev_priv->fifos[n].used=0; - DRM_DEBUG("%s: freeing fifo %d\n", __func__, n); + DRM_INFO("%s: freeing fifo %d\n", __func__, n); /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 9cd2c77..39b33ea 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -211,9 +211,11 @@ static void nouveau_nv10_context_switch( channel=0; dev_priv->cur_fifo=channel; + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000100); NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER)&0xE0FFFFFF)|(dev_priv->cur_fifo<<24)); - NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); + /* touch PGRAPH_CTX_SWITCH* here ? */ + NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100); } static void nouveau_pgraph_irq_handler(drm_device_t *dev) |
From: <ma...@ke...> - 2006-10-12 19:00:54
|
shared-core/nouveau_drv.h | 2 -- shared-core/nouveau_fifo.c | 4 ++-- shared-core/nouveau_irq.c | 11 ++++++++++- shared-core/nouveau_reg.h | 9 +++++++-- shared-core/nouveau_state.c | 5 ----- 5 files changed, 19 insertions(+), 12 deletions(-) New commits: diff-tree 7ef44b2b8dd1745f5b228e6161ebd989844c3088 (from a749d9d5b49ea0e402848bd6024e5c44826e784f) Author: Stephane Marchesin <mar...@ic...> Date: Thu Oct 12 17:31:49 2006 +0200 Still more work on the context switching code. diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 007bdd6..94b46ef 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -112,8 +112,6 @@ typedef struct drm_nouveau_private { drm_local_map_t *mmio; drm_local_map_t *fb; - int64_t fb_usable_size; - int cur_fifo; struct nouveau_object *fb_obj; diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index da9a863..1761bbe 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -227,7 +227,7 @@ static int nouveau_fifo_alloc(drm_device /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - if (dev_priv->card_type <= NV_04) + if (dev_priv->card_type <= NV_05) ctx_size=32; else ctx_size=128; @@ -239,7 +239,7 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(ctx_addr,init->put_base); NV_WRITE(ctx_addr+4,init->put_base); - if (dev_priv->card_type <= NV_04) + if (dev_priv->card_type <= NV_05) { // that's what is done in nvosdk, but that part of the code is buggy so... NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4); diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 39b33ea..4e58540 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -69,7 +69,15 @@ void nouveau_irq_postinstall(drm_device_ DRM_DEBUG("IRQ: postinst\n"); /* Enable PFIFO error reporting */ - NV_WRITE(NV_PFIFO_INTEN , NV_PFIFO_INTR_ERROR); + NV_WRITE(NV_PFIFO_INTEN , + NV_PFIFO_INTR_CACHE_ERROR | + NV_PFIFO_INTR_RUNOUT | + NV_PFIFO_INTR_RUNOUT_OVERFLOW | + NV_PFIFO_INTR_DMA_PUSHER | + NV_PFIFO_INTR_DMA_PT | + NV_PFIFO_INTR_SEMAPHORE | + NV_PFIFO_INTR_ACQUIRE_TIMEOUT + ); NV_WRITE(NV_PFIFO_INTSTAT, 0xFFFFFFFF); /* Enable PGRAPH interrupts */ @@ -279,6 +287,7 @@ static void nouveau_pgraph_irq_handler(d switch(dev_priv->card_type) { case NV_04: + case NV_05: nouveau_nv04_context_switch(dev); break; case NV_10: diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 2b723c7..ac7c932 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -75,7 +75,13 @@ #define NV_PFIFO_DMA_TIMESLICE 0x00002044 #define NV_PFIFO_INTSTAT 0x00002100 #define NV_PFIFO_INTEN 0x00002140 -# define NV_PFIFO_INTR_ERROR (1<<0) +# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0) +# define NV_PFIFO_INTR_RUNOUT (1<< 4) +# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8) +# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) +# define NV_PFIFO_INTR_DMA_PT (1<<16) +# define NV_PFIFO_INTR_SEMAPHORE (1<<20) +# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) #define NV_PFIFO_RAMHT 0x00002210 #define NV_PFIFO_RAMFC 0x00002214 #define NV_PFIFO_RAMRO 0x00002218 @@ -91,7 +97,6 @@ #define NV_PFIFO_CACH1_DMAPSH 0x00003220 #define NV_PFIFO_CACH1_DMAF 0x00003224 # define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 -# define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000 # define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008 # define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010 # define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018 diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index a015a0f..bd70aef 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -64,11 +64,6 @@ int nouveau_firstopen(struct drm_device DRM_INFO("%lld MB of video ram detected\n",nouveau_mem_fb_amount(dev)>>20); - if (dev_priv->card_type>=NV_40) - dev_priv->fb_usable_size=nouveau_mem_fb_amount(dev)-560*1024; - else - dev_priv->fb_usable_size=nouveau_mem_fb_amount(dev)-256*1024; - return 0; } |
From: <ma...@ke...> - 2006-10-12 19:13:01
|
shared-core/nouveau_irq.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) New commits: diff-tree a9c6c3f21d90257db94536f202b3a1f03896b2f7 (from 7ef44b2b8dd1745f5b228e6161ebd989844c3088) Author: Stephane Marchesin <mar...@ic...> Date: Thu Oct 12 21:18:55 2006 +0200 Oops. diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 4e58540..c3755d7 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -145,11 +145,11 @@ static void nouveau_fifo_irq_handler(drm DRM_DEBUG("NV: PFIFO interrupt! INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", status, chmode, chstat); - if (status & NV_PFIFO_INTR_ERROR) { + if (status & NV_PFIFO_INTR_CACHE_ERROR) { DRM_ERROR("NV: PFIFO error interrupt\n"); - status &= ~NV_PFIFO_INTR_ERROR; - NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_ERROR); + status &= ~NV_PFIFO_INTR_CACHE_ERROR; + NV_WRITE(NV_PFIFO_INTSTAT, NV_PFIFO_INTR_CACHE_ERROR); } if (status) { |
From: <dar...@ke...> - 2006-10-13 19:58:00
|
shared-core/nouveau_fifo.c | 8 ++++++++ 1 files changed, 8 insertions(+) New commits: diff-tree 4988074794531939ec0cb0ad183633b59e9ccff4 (from a9c6c3f21d90257db94536f202b3a1f03896b2f7) Author: Ben Skeggs <dar...@ii...> Date: Sat Oct 14 06:57:49 2006 +1100 Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals). Ch 1 GET now advances, but no ctx_switch. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 1761bbe..bd924f5 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -259,6 +259,10 @@ static int nouveau_fifo_alloc(drm_device #endif } + /* disable the pusher ? */ + NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0); + NV_WRITE(NV_PFIFO_CACH1_PSH0, 0); + /* enable the fifo dma operation */ NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); @@ -274,6 +278,10 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); + /* reenable the pusher ? */ + NV_WRITE(NV_PFIFO_CACH1_PSH0, 1); + NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 1); + /* reenable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000001); |
From: <ma...@ke...> - 2006-10-13 20:29:06
|
shared-core/nouveau_fifo.c | 20 ++++++++++++++++---- 1 files changed, 16 insertions(+), 4 deletions(-) New commits: diff-tree b509abe413f74bd08f6415dec8147bd07e78a84b (from 4988074794531939ec0cb0ad183633b59e9ccff4) Author: Stephane Marchesin <mar...@ic...> Date: Fri Oct 13 22:35:22 2006 +0200 Fix the fifo context size on nv10, nv20 and nv30. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index bd924f5..9615e08 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -227,10 +227,22 @@ static int nouveau_fifo_alloc(drm_device /* disable the fifo caches */ NV_WRITE(NV_PFIFO_CACHES, 0x00000000); - if (dev_priv->card_type <= NV_05) - ctx_size=32; - else - ctx_size=128; + switch(dev_priv->card_type) + { + case NV_03: + case NV_04: + case NV_05: + ctx_size=32; + break; + case NV_10: + case NV_20: + case NV_30: + ctx_size=64; + case NV_40: + case G_70: + default: + ctx_size=128; + } ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size; // clear the fifo context |
From: <dar...@ke...> - 2006-10-16 19:12:56
|
shared-core/nouveau_reg.h | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+) New commits: diff-tree 95486bbde05ae51975c4d51fd194111788edee9a (from 93fee5cf222ad6d97e0dcb85e13a8d8b84dba81f) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 06:12:18 2006 +1100 Some info on NV40's RAMFC diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index ac7c932..c74feeb 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -178,4 +178,26 @@ #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) +/* RAMFC offsets */ +#define NV40_RAMFC_DMA_PUT 0x00 +#define NV40_RAMFC_DMA_GET 0x04 +#define NV40_RAMFC_REF_CNT 0x08 +#define NV40_RAMFC_DMA_INSTANCE 0x0C +#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10 +#define NV40_RAMFC_DMA_STATE 0x14 +#define NV40_RAMFC_DMA_FETCH 0x18 +#define NV40_RAMFC_ENGINE 0x1C +#define NV40_RAMFC_PULL1_ENGINE 0x20 +#define NV40_RAMFC_ACQUIRE_VALUE 0x24 +#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28 +#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C +#define NV40_RAMFC_SEMAPHORE 0x30 +#define NV40_RAMFC_DMA_SUBROUTINE 0x34 +#define NV40_RAMFC_GRCTX_INSTANCE_32E0 /* guess */ 0x38 +#define NV40_RAMFC_DMA_TIMESLICE 0x3C +#define NV40_RAMFC_UNK_40 0x40 +#define NV40_RAMFC_UNK_44 0x44 +#define NV40_RAMFC_UNK_48 0x48 +#define NV40_RAMFC_2088 0x4C +#define NV40_RAMFC_3300 0x50 |
From: <dar...@ke...> - 2006-10-17 01:34:13
|
shared-core/nouveau_fifo.c | 7 +++++-- shared-core/nouveau_object.c | 6 ++---- 2 files changed, 7 insertions(+), 6 deletions(-) New commits: diff-tree 4b43ee63f90c93701c9f1cdf7fefd1816b316d33 (from 98e718d48fcd166accf1af3c017c34e331ab09cb) Author: Ben Skeggs <dar...@ii...> Date: Tue Oct 17 12:33:49 2006 +1100 NV40: *Now* fifo ctx switching works for me.. Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d015d42..5a7b863 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -92,12 +92,15 @@ static void nouveau_fifo_init(drm_device ((dev_priv->objs.ht_bits - 9) << 16) | (dev_priv->objs.ht_base >> 8) ); - dev_priv->ramfc_offset=0x12000; - dev_priv->ramro_offset=0x11200; + /* RAMFC needs to be at RAMIN+0x20000 on NV40, I currently don't know + * how to move it.. + */ + dev_priv->ramfc_offset=0x20000; if (dev_priv->card_type < NV_40) NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */ else NV_WRITE(0x2220, 0x30002); + dev_priv->ramro_offset=0x11200; NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */ NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000); diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 5f11cfa..18c5076 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -303,10 +303,8 @@ void nouveau_hash_table_init(drm_device_ dev_priv->objs.inst_bmap = drm_calloc (1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER); - /* clear the hash table */ - ht_start = NV_RAMIN+dev_priv->objs.ht_base; - ht_end = ht_start + dev_priv->objs.ht_size; - for (i=ht_start; i<ht_end; i+=4) + /* clear all of RAMIN */ + for (i=0x00700000; i<0x00800000; i+=4) NV_WRITE(i, 0x00000000); } |
From: <dar...@ke...> - 2006-10-17 14:08:14
|
shared-core/nouveau_irq.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) New commits: diff-tree 725984364bd899c2dee1ca9b44f56fc70ccba3ad (from 55de3f763f0de66b99f1afde9872f0072a84a9e3) Author: Ben Skeggs <dar...@ii...> Date: Wed Oct 18 01:07:48 2006 +1100 Oops, we have more than 4 subchannels.. diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index af6109e..6de4a5e 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -161,7 +161,7 @@ static void nouveau_fifo_irq_handler(drm } DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n", - channel, (c1method >> 13) & 3, + channel, (c1method >> 13) & 7, c1method & 0x1ffc, c1data ); |
From: <dar...@ke...> - 2006-10-17 15:38:19
|
shared-core/nouveau_fifo.c | 44 +++++++++++++++++++++++++++++++++++++++----- shared-core/nouveau_reg.h | 8 ++++++++ 2 files changed, 47 insertions(+), 5 deletions(-) New commits: diff-tree b5cf0d635c81d2c99510ce5e3f67f4aa593cd6d7 (from 725984364bd899c2dee1ca9b44f56fc70ccba3ad) Author: Ben Skeggs <dar...@ii...> Date: Wed Oct 18 02:37:19 2006 +1100 Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 5a7b863..5c32866 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -238,10 +238,10 @@ static void nouveau_context_init(drm_dev } +#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) static void nouveau_nv40_context_init(drm_device_t *dev, drm_nouveau_fifo_alloc_t *init) { -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val)) drm_nouveau_private_t *dev_priv = dev->dev_private; uint32_t fifoctx; int i; @@ -260,9 +260,37 @@ static void nouveau_nv40_context_init(dr RAMFC_WR(DMA_SUBROUTINE, init->put_base); RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */ RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); -#undef RAMFC_WR } +static void nouveau_nv40_context_save(drm_device_t *dev) +{ + drm_nouveau_private_t *dev_priv = dev->dev_private; + uint32_t fifoctx; + int channel; + + channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1); + fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128; + + RAMFC_WR(DMA_PUT , NV_READ(NV_PFIFO_CACH1_DMAP)); + RAMFC_WR(DMA_GET , NV_READ(NV_PFIFO_CACH1_DMAG)); + RAMFC_WR(REF_CNT , NV_READ(NV_PFIFO_CACH1_REF_CNT)); + RAMFC_WR(DMA_INSTANCE , NV_READ(NV_PFIFO_CACH1_DMAI)); + RAMFC_WR(DMA_DCOUNT , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT)); + RAMFC_WR(DMA_STATE , NV_READ(NV_PFIFO_CACH1_DMAS)); + //fetch + RAMFC_WR(ENGINE , NV_READ(NV_PFIFO_CACH1_ENG)); + RAMFC_WR(PULL1_ENGINE , NV_READ(NV_PFIFO_CACH1_PUL1)); + RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE)); + RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP)); + RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT)); + RAMFC_WR(SEMAPHORE , NV_READ(NV_PFIFO_CACH1_SEMAPHORE)); + RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV_PFIFO_CACH1_DMAG)); + RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE)); + RAMFC_WR(DMA_TIMESLICE , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF); + RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4)); +} +#undef RAMFC_WR + /* allocates and initializes a fifo for user space consumption */ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp) { @@ -314,8 +342,16 @@ static int nouveau_fifo_alloc(drm_device if (dev_priv->card_type < NV_40) nouveau_context_init(dev, init); - else + else { + /* Save current channel's state to it's RAMFC entry */ + nouveau_nv40_context_save(dev); + /* Construct inital RAMFC for new channel, I'm not entirely + * sure this is needed if we activate the channel immediately. + * My understanding is that the GPU will fill RAMFC itself + * when it switches away from the channel + */ nouveau_nv40_context_init(dev, init); + } /* enable the fifo dma operation */ NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel)); @@ -323,7 +359,6 @@ static int nouveau_fifo_alloc(drm_device NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base); NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base); -if (init->channel == 0) { // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF); if (dev_priv->card_type >= NV_40) @@ -346,7 +381,6 @@ if (init->channel == 0) { #else NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4); #endif -} NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001); NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index b393e87..f15b621 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -162,11 +162,19 @@ #define NV_PFIFO_CACH1_DMAC 0x00003230 #define NV_PFIFO_CACH1_DMAP 0x00003240 #define NV_PFIFO_CACH1_DMAG 0x00003244 +#define NV_PFIFO_CACH1_REF_CNT 0x00003248 #define NV_PFIFO_CACH1_PUL0 0x00003250 #define NV_PFIFO_CACH1_PUL1 0x00003254 #define NV_PFIFO_CACH1_HASH 0x00003258 +#define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260 +#define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264 +#define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268 +#define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C #define NV_PFIFO_CACH1_GET 0x00003270 #define NV_PFIFO_CACH1_ENG 0x00003280 +#define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0 +#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 +#define NV40_PFIFO_UNK32E4 0x000032E4 #define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8)) #define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8)) #define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8)) |
From: <ma...@ke...> - 2006-11-04 14:48:18
|
shared-core/nouveau_drm.h | 7 ++++++- shared-core/nouveau_object.c | 40 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 43 insertions(+), 4 deletions(-) New commits: diff-tree 3ea0500be1ab7a058c90be35b5d8d2be26692f6a (from b5cf0d635c81d2c99510ce5e3f67f4aa593cd6d7) Author: Stephane Marchesin <mar...@ic...> Date: Sat Nov 4 16:56:10 2006 +0100 Move the context object creation flag handling to the drm. diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index ed87f5c..9e996de 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -37,10 +37,15 @@ typedef struct drm_nouveau_fifo_alloc { } drm_nouveau_fifo_alloc_t; +#define NV_DMA_CONTEXT_FLAGS_PATCH_ROP_AND 0x1 +#define NV_DMA_CONTEXT_FLAGS_PATCH_SRCCOPY 0x2 +#define NV_DMA_CONTEXT_FLAGS_CLIP_ENABLE 0x4 +#define NV_DMA_CONTEXT_FLAGS_MONO 0x8 + typedef struct drm_nouveau_object_init { uint32_t handle; int class; - uint32_t flags0, flags1, flags2; + uint32_t flags; /* these are object handles */ uint32_t dma0; uint32_t dma1; diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index 78a4b78..b539ee6 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -427,7 +427,7 @@ struct nouveau_object *nouveau_dma_objec set to 0? */ static struct nouveau_object *nouveau_context_object_create(drm_device_t* dev, - int class, uint32_t flags0, uint32_t flags1, uint32_t flags2, + int class, uint32_t flags, struct nouveau_object *dma0, struct nouveau_object *dma1, struct nouveau_object *dma_notifier) @@ -435,6 +435,40 @@ static struct nouveau_object *nouveau_co drm_nouveau_private_t *dev_priv=dev->dev_private; struct nouveau_object *obj; uint32_t d0, d1, dn; + uint32_t flags0,flags1,flags2; + flags0=0;flags1=0;flags2=0; + + if (dev_priv->card_type >= NV_40) { + if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_ROP_AND) + flags0 |= 0x02080000; + else if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_SRCCOPY) + flags0 |= 0x02080000; + if (flags & NV_DMA_CONTEXT_FLAGS_CLIP_ENABLE) + flags0 |= 0x00020000; +#ifdef __BIG_ENDIAN + if (flags & NV_DMA_CONTEXT_FLAGS_MONO) + flags1 |= 0x01000000; + flags2 |= 0x01000000; +#else + if (flags & NV_DMA_CONTEXT_FLAGS_MONO) + flags1 |= 0x02000000; +#endif + } else { + if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_ROP_AND) + flags0 |= 0x01008000; + else if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_SRCCOPY) + flags0 |= 0x01018000; + if (flags & NV_DMA_CONTEXT_FLAGS_CLIP_ENABLE) + flags0 |= 0x00002000; +#ifdef __BIG_ENDIAN + flags0 |= 0x00080000; + if (flags & NV_DMA_CONTEXT_FLAGS_MONO) + flags1 |= 0x00000001; +#else + if (flags & NV_DMA_CONTEXT_FLAGS_MONO) + flags1 |= 0x00000002; +#endif + } DRM_DEBUG("class=%x, dma0=%08x, dma1=%08x, dman=%08x\n", class, @@ -536,8 +570,8 @@ int nouveau_ioctl_object_init(DRM_IOCTL_ return DRM_ERR(EINVAL); } - obj = nouveau_context_object_create(dev, init.class, init.flags0, - init.flags1, init.flags2, dma0, dma1, dman); + obj = nouveau_context_object_create(dev, init.class, init.flags, + dma0, dma1, dman); if (!obj) return DRM_ERR(ENOMEM); |
From: <ma...@ke...> - 2006-11-04 18:32:16
|
shared-core/drm_pciids.txt | 40 ++++++++++++++++++++-------------------- shared-core/nouveau_drm.h | 4 ++++ shared-core/nouveau_state.c | 14 ++++++++++++++ 3 files changed, 38 insertions(+), 20 deletions(-) New commits: diff-tree 06639801ce1d515f790739a70b051498c8615288 (from 3ea0500be1ab7a058c90be35b5d8d2be26692f6a) Author: Stephane Marchesin <mar...@ic...> Date: Sat Nov 4 20:39:59 2006 +0100 Add some getparams. diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index a6e917a..f1d8731 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -494,21 +494,21 @@ 0x10de 0x0171 NV_10 "GeForce4 MX 440" 0x10de 0x0172 NV_10 "GeForce4 MX 420" 0x10de 0x0173 NV_10 "GeForce4 MX 440-SE" -0x10de 0x0178 NV_20 "Quadro4 550 XGL" +0x10de 0x0178 NV_10 "Quadro4 550 XGL" 0x10de 0x017a NV_10 "Quadro NVS" 0x10de 0x0181 NV_10 "GeForce4 MX 440 with AGP8X" 0x10de 0x0182 NV_10 "GeForce4 MX 440SE with AGP8X" 0x10de 0x0183 NV_10 "GeForce4 MX 420 with AGP8X" 0x10de 0x0185 NV_10 "GeForce4 MX 4000" -0x10de 0x0188 NV_20 "Quadro4 580 XGL" +0x10de 0x0188 NV_10 "Quadro4 580 XGL" 0x10de 0x018a NV_10 "Quadro NVS with AGP8X" -0x10de 0x018b NV_20 "Quadro4 380 XGL" +0x10de 0x018b NV_10 "Quadro4 380 XGL" 0x10de 0x018c NV_10 "Quadro NVS 50 PCI" 0x10de 0x01f0 NV_10|NV_NFORCE2 "GeForce4 MX Integrated GPU" 0x10de 0x0200 NV_20 "GeForce3" 0x10de 0x0201 NV_20 "GeForce3 Ti 200" 0x10de 0x0202 NV_20 "GeForce3 Ti 500" -0x10de 0x0203 NV_10 "Quadro DCC" +0x10de 0x0203 NV_20 "Quadro DCC" 0x10de 0x0250 NV_20 "GeForce4 Ti 4600" 0x10de 0x0251 NV_20 "GeForce4 Ti 4400" 0x10de 0x0252 NV_20 "NV25" @@ -535,7 +535,7 @@ 0x10de 0x0323 NV_30 "GeForce FX 5200LE" 0x10de 0x0326 NV_30 "GeForce FX 5500" 0x10de 0x0327 NV_30 "GeForce FX 5100" -0x10de 0x032a NV_10 "Quadro NVS 280 PCI" +0x10de 0x032a NV_30 "Quadro NVS 280 PCI" 0x10de 0x032b NV_30 "Quadro FX 500/FX 600" 0x10de 0x032f NV_30 "NV34GL" 0x10de 0x0330 NV_30 "GeForce FX 5900 Ultra" @@ -558,13 +558,13 @@ 0x10de 0x0043 NV_40 "NV40" 0x10de 0x0045 NV_40 "GeForce 6800 GT" 0x10de 0x0049 NV_40 "NV40GL" -0x10de 0x004e NV_30 "Quadro FX 4000" +0x10de 0x004e NV_40 "Quadro FX 4000" 0x10de 0x00c0 NV_40 "NV41" 0x10de 0x00c1 NV_40 "GeForce 6800" 0x10de 0x00c2 NV_40 "GeForce 6800 LE" -0x10de 0x00cc NV_30 "Quadro FX Go1400" -0x10de 0x00cd NV_30 "Quadro FX 3450/4000 SDI" -0x10de 0x00ce NV_30 "Quadro FX 1400" +0x10de 0x00cc NV_40 "Quadro FX Go1400" +0x10de 0x00cd NV_40 "Quadro FX 3450/4000 SDI" +0x10de 0x00ce NV_40 "Quadro FX 1400" 0x10de 0x0140 NV_40 "GeForce 6600 GT" 0x10de 0x0141 NV_40 "GeForce 6600" 0x10de 0x0142 NV_40 "NV43" @@ -573,13 +573,13 @@ 0x10de 0x014b NV_40 "NV43" 0x10de 0x014c NV_40 "NV43GL" 0x10de 0x014d NV_40 "NV43GL" -0x10de 0x014e NV_30 "Quadro FX 540" +0x10de 0x014e NV_40 "Quadro FX 540" 0x10de 0x014f NV_40 "GeForce 6200" 0x10de 0x0160 NV_40 "NV44" 0x10de 0x0161 NV_40 "GeForce 6200 TurboCache(TM)" 0x10de 0x0162 NV_40 "NV44" 0x10de 0x0163 NV_40 "NV44" -0x10de 0x0165 NV_10 "Quadro NVS 285" +0x10de 0x0165 NV_40 "Quadro NVS 285" 0x10de 0x016e NV_40 "NV44GL" 0x10de 0x0220 NV_40 "NV44" 0x10de 0x0221 NV_40 "NV44" @@ -601,7 +601,7 @@ 0x10de 0x00f9 NV_40 "GeForce 6800 Ultra" 0x10de 0x00f9 NV_40 "GeForce 6800 GT" 0x10de 0x00f9 NV_40 "GeForce 6800 Series GPU" -0x10de 0x0091 NV_10 "GeForce 7800 GTX" +0x10de 0x0091 G_70 "GeForce 7800 GTX" 0x10de 0x00fa NV_30 "GeForce PCX 5750" 0x10de 0x00fa NV_30 "GeForce PCX 5750" 0x10de 0x00fb NV_30 "GeForce PCX 5900" @@ -609,7 +609,7 @@ 0x10de 0x00fc NV_30 "GeForce PCX 5300" 0x10de 0x00fc NV_30 "Quadro FX 330" 0x10de 0x00fc NV_30 "GeForce PCX 5300" -0x10de 0x00fd NV_10 "Quadro NVS 280 PCI-E" +0x10de 0x00fd NV_30 "Quadro NVS 280 PCI-E" 0x10de 0x00fd NV_30 "Quadro FX 330" 0x10de 0x00fd NV_10 "Quadro PCI-E Series" 0x10de 0x00fe NV_30 "Quadro FX 1300" @@ -652,21 +652,21 @@ 0x10de 0x00c9 NV_30 "GeForce Go 6800 Ultra" 0x10de 0x00cc NV_30 "Quadro FX Go1400" 0x10de 0x0140 NV_40 "NV43" -0x10de 0x0144 NV_30 "GeForce Go 6600" +0x10de 0x0144 NV_40 "GeForce Go 6600" 0x10de 0x0147 NV_40 "NV43" -0x10de 0x0148 NV_30 "GeForce Go 6600" +0x10de 0x0148 NV_40 "GeForce Go 6600" 0x10de 0x0149 NV_40 "NV43" 0x10de 0x014c NV_40 "NV43GL" -0x10de 0x0164 NV_30 "GeForce Go 6200" -0x10de 0x0167 NV_30 "GeForce Go 6200" +0x10de 0x0164 NV_40 "GeForce Go 6200" +0x10de 0x0167 NV_40 "GeForce Go 6200" 0x10de 0x0169 NV_40 "NV44M" 0x10de 0x016b NV_40 "NV44GLM" 0x10de 0x016c NV_40 "NV44GLM" 0x10de 0x016d NV_40 "NV44GLM" 0x10de 0x0228 NV_40 "NV44M" -0x10de 0x0091 NV_10 "NVIDIA GeForce 7800 GTX" -0x10de 0x0092 NV_10 "NVIDIA GeForce 7800 GT" -0x10de 0x009d NV_30 "NVIDIA Quadro FX 4500" +0x10de 0x0091 G_70 "NVIDIA GeForce 7800 GTX" +0x10de 0x0092 G_70 "NVIDIA GeForce 7800 GT" +0x10de 0x009d G_70 "NVIDIA Quadro FX 4500" 0x10de 0x0240 NV_40 "NVIDIA GeForce 6150" 0x10de 0x0241 NV_40 "NVIDIA GeForce 6150 LE" 0x10de 0x0242 NV_40 "NVIDIA GeForce 6100" diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h index 9e996de..865dbe9 100644 --- a/shared-core/nouveau_drm.h +++ b/shared-core/nouveau_drm.h @@ -84,6 +84,10 @@ typedef struct drm_nouveau_mem_free { } drm_nouveau_mem_free_t; +/* FIXME : maybe unify {GET,SET}PARAMs */ +#define NOUVEAU_GETPARAM_PCI_VENDOR 3 +#define NOUVEAU_GETPARAM_PCI_DEVICE 4 +#define NOUVEAU_GETPARAM_BUS_TYPE 5 typedef struct drm_nouveau_getparam { unsigned int param; unsigned int value; diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c index bd70aef..1901f08 100644 --- a/shared-core/nouveau_state.c +++ b/shared-core/nouveau_state.c @@ -103,6 +103,20 @@ int nouveau_ioctl_getparam(DRM_IOCTL_ARG sizeof(getparam)); switch (getparam.param) { + case NOUVEAU_GETPARAM_PCI_VENDOR: + getparam.value=dev->pci_vendor; + break; + case NOUVEAU_GETPARAM_PCI_DEVICE: + getparam.value=dev->pci_device; + break; + case NOUVEAU_GETPARAM_BUS_TYPE: + if (drm_device_is_agp(dev)) + getparam.value=NV_AGP; + else if (drm_device_is_pcie(dev)) + getparam.value=NV_PCIE; + else + getparam.value=NV_PCI; + break; default: DRM_ERROR("unknown parameter %d\n", getparam.param); return DRM_ERR(EINVAL); |
From: <ai...@ke...> - 2006-11-05 09:40:56
|
linux-core/Makefile.kernel | 1 linux-core/nouveau_drv.c | 3 + linux-core/nouveau_ioc32.c | 73 +++++++++++++++++++++++++++++++++++++++++++++ shared-core/nouveau_drv.h | 3 + 4 files changed, 80 insertions(+) New commits: diff-tree 94ab96c4d8203c236c6a5a8d8a6a761ccf808662 (from 665c8385c7865dcc4f92b9c212d6e2b35d7fa9f0) Author: Dave Airlie <airlied@ppcg5.localdomain> Date: Sun Nov 5 20:38:44 2006 +1100 nouveau: add compat ioc32 support diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel index 950259b..71605de 100644 --- a/linux-core/Makefile.kernel +++ b/linux-core/Makefile.kernel @@ -35,6 +35,7 @@ radeon-objs += radeon_ioc32.o mga-objs += mga_ioc32.o r128-objs += r128_ioc32.o i915-objs += i915_ioc32.o +nouveau-objs += nouveau_ioc32.o endif obj-m += drm.o diff --git a/linux-core/nouveau_drv.c b/linux-core/nouveau_drv.c index 8ad1d84..57b55ce 100644 --- a/linux-core/nouveau_drv.c +++ b/linux-core/nouveau_drv.c @@ -60,6 +60,9 @@ static struct drm_driver driver = { .mmap = drm_mmap, .poll = drm_poll, .fasync = drm_fasync, +#if defined(CONFIG_COMPAT) && LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9) + .compat_ioctl = nouveau_compat_ioctl, +#endif }, .pci_driver = { .name = DRIVER_NAME, diff --git a/linux-core/nouveau_ioc32.c b/linux-core/nouveau_ioc32.c new file mode 100644 index 0000000..a752a58 --- /dev/null +++ b/linux-core/nouveau_ioc32.c @@ -0,0 +1,73 @@ +/** + * \file mga_ioc32.c + * + * 32-bit ioctl compatibility routines for the MGA DRM. + * + * \author Dave Airlie <ai...@li...> with code from patches by Egbert Eich + * + * + * Copyright (C) Paul Mackerras 2005 + * Copyright (C) Egbert Eich 2003,2004 + * Copyright (C) Dave Airlie 2005 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <linux/compat.h> +#include <linux/ioctl32.h> + +#include "drmP.h" +#include "drm.h" + +#include "nouveau_drm.h" + +/** + * Called whenever a 32-bit process running under a 64-bit kernel + * performs an ioctl on /dev/dri/card<n>. + * + * \param filp file pointer. + * \param cmd command. + * \param arg user argument. + * \return zero on success or negative number on failure. + */ +long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + unsigned int nr = DRM_IOCTL_NR(cmd); + drm_ioctl_compat_t *fn = NULL; + int ret; + + if (nr < DRM_COMMAND_BASE) + return drm_compat_ioctl(filp, cmd, arg); + +#if 0 + if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) + fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE]; +#endif + lock_kernel(); /* XXX for now */ + if (fn != NULL) + ret = (*fn)(filp, cmd, arg); + else + ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); + unlock_kernel(); + + return ret; +} diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h index 4b35e6d..f579026 100644 --- a/shared-core/nouveau_drv.h +++ b/shared-core/nouveau_drv.h @@ -171,6 +171,9 @@ extern void nouveau_irq_preinstal extern void nouveau_irq_postinstall(drm_device_t*); extern void nouveau_irq_uninstall(drm_device_t*); +extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); + #if defined(__powerpc__) #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) ) #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) ) |
From: <dar...@ke...> - 2006-11-05 18:48:40
|
shared-core/nouveau_object.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) New commits: diff-tree 0c34d0f31a691bb649ed69f19e93fc1a723aa1d4 (from 94ab96c4d8203c236c6a5a8d8a6a761ccf808662) Author: Ben Skeggs <dar...@ii...> Date: Mon Nov 6 05:46:03 2006 +1100 Leave the bottom 64kb of RAMIN untouched. The binary driver will screw up either it's init or shutdown, leaving the screen(s) in an unusable state without this. Something important in there? diff --git a/shared-core/nouveau_object.c b/shared-core/nouveau_object.c index b539ee6..935297f 100644 --- a/shared-core/nouveau_object.c +++ b/shared-core/nouveau_object.c @@ -302,8 +302,12 @@ void nouveau_hash_table_init(drm_device_ dev_priv->objs.inst_bmap = drm_calloc (1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER); - /* clear all of RAMIN */ - for (i=0x00700000; i<0x00800000; i+=4) + /* clear all of RAMIN + * NOTE: except the bottom 0x10000 bytes, the binary driver doesn't + * like this and will die either sometime during init, or during + * shutdown - leaving the screen in an unusable state... + */ + for (i=0x00710000; i<0x00800000; i+=4) NV_WRITE(i, 0x00000000); } |
From: <ma...@ke...> - 2006-11-10 00:10:05
|
shared-core/nouveau_mem.c | 3 +++ 1 files changed, 3 insertions(+) New commits: diff-tree 1123ab089075af3141c794696ec394fa46b4353f (from f7affda35bb0c47fbc973725e05847669e215d46) Author: Stephane Marchesin <mar...@ic...> Date: Fri Nov 10 02:18:38 2006 +0100 Fix memory detection on TNT2 M64/TNT2 vanta. diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 91fc604..897badd 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -234,6 +234,9 @@ uint64_t nouveau_mem_fb_amount(struct dr break; case NV_04: case NV_05: + if (NV_READ(NV03_BOOT_0) & 0x00000100) { + return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024; + } else switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT) { case NV04_BOOT_0_RAM_AMOUNT_32MB: |
From: <dar...@ke...> - 2006-11-16 21:05:44
|
shared-core/nouveau_fifo.c | 2 +- shared-core/nouveau_irq.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) New commits: diff-tree 18bba3fa29187bb5122ed057989203dc05bc46aa (from 2fd812f8ef8adb09fd8d17cab869f9fc8b047d75) Author: Ben Skeggs <dar...@ii...> Date: Fri Nov 17 08:05:23 2006 +1100 Dump some useful info when a PGRAPH error occurs. The "channel" detect doesn't work on my nv40, but the rest seems to produce sane info. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index c662165..73c4e9f 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -536,7 +536,7 @@ void nouveau_fifo_cleanup(drm_device_t* DRM_DEBUG("clearing FIFO enables from filp\n"); for(i=0;i<nouveau_fifo_number(dev);i++) - if (dev_priv->fifos[i].filp==filp) + if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp==filp) nouveau_fifo_free(dev,i); /* check we still point at an active channel */ diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 6de4a5e..9131125 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -306,8 +306,33 @@ static void nouveau_pgraph_irq_handler(d } if (status & NV_PGRAPH_INTR_ERROR) { + uint32_t nsource, nstatus, instance; + uint32_t address; + uint32_t channel; + uint32_t method, subc, data; + DRM_ERROR("NV: PGRAPH error interrupt\n"); + nstatus = NV_READ(0x00400104); + nsource = NV_READ(0x00400108); + DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus); + + instance = NV_READ(0x00400158); + DRM_DEBUG("instance:0x%08x\n", instance); + + address = NV_READ(0x400704); + data = NV_READ(0x400708); + channel = (address >> 20) & 0x1F; + subc = (address >> 16) & 0x7; + method = address & 0x1FFC; + DRM_DEBUG("NV: 0x400704 = 0x%08x\n", address); + DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -" + "Method 0x%04x, Data 0x%08x\n", + channel, subc, + NV_READ(0x400160+subc*4) & 0xFFFF, + method, data + ); + status &= ~NV_PGRAPH_INTR_ERROR; NV_WRITE(NV_PGRAPH_INTSTAT, NV_PGRAPH_INTR_ERROR); } |
From: <dar...@ke...> - 2006-11-21 00:42:11
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shared-core/nouveau_irq.c | 2 ++ 1 files changed, 2 insertions(+) New commits: diff-tree adf71cb29b72b7d199f737b7b00eb7e80939ea4b (from 9ac7a8b0b4c0431b605c3f8d0b4a696903010c51) Author: Ben Skeggs <dar...@ii...> Date: Tue Nov 21 11:41:46 2006 +1100 Don't spam dmesg if PMC_INTSTAT is 0 diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c index 9131125..160016e 100644 --- a/shared-core/nouveau_irq.c +++ b/shared-core/nouveau_irq.c @@ -385,6 +385,8 @@ irqreturn_t nouveau_irq_handler(DRM_IRQ_ uint32_t status; status = NV_READ(NV_PMC_INTSTAT); + if (!status) + return IRQ_NONE; DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status); |