ACMgen 1.2

In this release we have included a new generator for verilog code. On the old machine the RRBB, OWBB and OWRRBB policies were supported. However, besides the fact the that code could be simulated, the hardware synthesis of was not feasible.

On this new version, only the RRBB policy is supported. Simulation has been performed for a number of different sizes (from 3 to 9) and in all cases freshness and coherence properties were performed.

Besides that, the code has been tested with a synthesis tool. Using the Altera Quartus II (the free edition), it was possible to make synthesis.

Hope this is useful for somebody.