Search Results for "ascii diagram"

Generate UML diagram from textual description. PlantUML is not affected by the log4j vulnerability. The easiest way to test PlantUML is in an online solution that has PlantUML embedded, such as our online server. After testing, you may want to install PlantUML locally. Run (or have your software call) PlantUML, using sequenceDiagram.txt as input. The output is an image, which either appears in the other software, or is written to an image file on disk. Diagrams are defined using a simple...

This is nomnoml, a tool for drawing UML diagrams based on a simple syntax. It tries to keep its syntax visually as close as possible to the generated UML diagram without resorting to ASCII drawings. The nomnoml javascript library can render diagrams on your web page. The only dependency is graphite. Install nomnoml using either npm or good old script inclusion. In the SVG output the node name is attached to SVG shapes and g containers with data-name attribute. You can use this to implement...

Svgbob can create a nice graphical representation of your text diagrams. Svgbob provides a cli that takes text as input and creates an svg image as an output. Svgbob is a diagramming model which uses a set of typing characters to approximate the intended shape.

The Ensemble Verification System (EVS) is designed to verify ensemble forecasts of hydrologic and hydrometeorological variables, such as temperature, precipitation, and streamflow, issued at discrete forecast locations (points or areas).

This tool generates timing diagrams for documenting hardware design. It reads the description from a text file with a simple syntax. It generates vector graphic (EPS, SVG or EMF format). It can be used in command line mode or with a GUI. It is written in Python and works on any platform.

PLC-EMU is a Programmable Logic Controller EMUlator for automation applications on linux with digital/analog IO cards, with C functions, Ladder Diagrams,or IEC61131-compliant Instruction List/Structured Text. It is a cheap and open alternative to PLCs.

A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.

Version 1.1.5 - Added: Added the ability to edit the EMV panel - You can change which tags show, and what order they are in - Added: Tag 9F10 (Issuer Application Data) to which also includes CVR (a subtag of 9F10) - Added: Menu link to the homepage (sourceforge) - Fixed: 9F07/AUC had the wrong tag details - Fixed: File>Close now saves notes and config updates before exiting - Fixed: Tag 95/TVR title had a spelling mistake - Fixed: Homepage wasn't populating EMV page names -...

Diagram editor for plain text files

ChronoSVG generates a timing diagram, as used in electrical devices documentations, from a simple and intuitive ASCII source file. The output file is in SVG format, and makes use of CSS to defer the styling details to presentation time.

An ASCII UML class diagram interpreter and code generation framework.