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advzip: "Failed tell" error for ZIPs larger than 2GB in size

Ah, good points, I forgot about overflows. The load is small, but I'd have thought that it shouldn't affect clock speeds much? The AVX offset is at default ("Auto"). I'm not sure what value it selects - the motherboard manual doesn't say much either: "If set to Auto, BIOS will configure this setting automatically". I could select a value I suppose, but I've been trying to test at stock settings. I retried with the modified program: #include <immintrin.h> int main(int argc, char** argv) { switch (argv[1][0])...

Largely the same result unfortunately. I decided to set up a test using the program: #include <immintrin.h> int main(int argc, char** argv) { switch (argv[1][0]) { case 'i': { // scalar int int n = 1, m = 2; for (int i = 0; i<100; i++) for (int j = 0; j<1e9; j++) { n += n; m += m; } return n + m; } case 'f': { // scalar float float n = 1, m = 2; for (int i = 0; i<100; i++) for (int j = 0; j<1e9; j++) { n += n; m += m; } return n + m; } case 'x': { // 128b int __m128i n = _mm_set1_epi8(1), m = _mm_set1_epi8(2);...

I notice that in CPU-Z's 'Clocks' window, cores 2 and 4 are marked in red, so I wonder if it's managed to detect something there. I tried WinRAR's benchmark, setting affinity to one core, and leaving it for a while, and repeating for each core. Screenshot of HWiNFO attached. This benchmark doesn't seem to stress the CPU much, as the CPU fan didn't spin up at all, and none of cores seem to really go beyond 4.1GHz. Despite some of the readings showing a higher max clock rate, I suspect they may be...

Oops, my mistake, so only 2 cores disabled on 7820X, but unknown as to which ones. The core numbers do all match up: Task Manager, HWiNFO and 7z's affinity mask (I was originally setting affinity using Task Manager). Using -stm3 -mmt2 I can see the first two threads in Task Manager use all the CPU, and HWiNFO shows Core 0's frequency scaling up, and I've repeated this for all cores with the same result. I left HWiNFO running whilst I ran test_affinity, and it does show cores 2 and 4 boosting to 4.5GHz,...

That's rather interesting. Do you think it may depend on the positioning of the cores and which slice of L3 the data is stored in? From what I know, the mesh can require 1 or 2 hops to get the data. I believe the Skylake-X LCC die supports 12 cores, so presumably 4 of them are disabled on the 8 core CPU. I don't know whether it's possible to determine the physical positioning of the cores and how much of an effect that'd have. You also don't think that turbo would distort the clock timings a bit?...

Results attached

CPU-Z screenshots attached. Interestingly, the DRAM Frequency seems to jump around, usually at 1700MHz, but sometimes going down to 739MHz - some powersaving feature? (I never knew DRAM would throttle down, though it's usually at the right speed)