Activity for liu zhi qiang
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liu zhi qiang posted a comment on discussion Getting Started
the issue has been solved, hi,Powerlink-Team-Kalycito, thank you for your strong support.
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Hi, Powerlink-team Kalycito , Would you please help me,sir?thanks
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Hello Powerlink-team Kalycito , Is "TIMER_PULSE_IRQ" pin of openMAC IP a “Timer interruption” and it be triggered periodically？ thanks a lot for your help.
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Hello Powerlink-team Kalycito , Thanks for you support me. 1,I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program,Can you tell me when is the #61 interruption (from openMAC IP to PS7) triggered in "Zynq Hybrid design"?and what is its role? 2,I tried to use the "interrupt" pin of "Axi Ethernet IP" to trigger the #61 interruption of...
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Hello Powerlink-team Kalycito , Thanks for you support me. 1,I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program,Can you tell me when is the #61 interruption (from openMAC IP to PS7) triggered in "Zynq Hybrid design"?and what is its role? 2,I used the "interrupt" pin of "Axi Ethernet IP" to trigger the #61 interruption of PS7,but...
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program,Can you tell me when is the #61 interruption (from openMAC IP to PS7) triggered in "Zynq Hybrid design"?and what is its role? Now,the CN (demo_cn_console in Linux platform) can link to my MN successfully,but it takes about 20 minutes. What are the...
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program,Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"?and what is its role? Now,the CN (demo_cn_console in Linux platform) can link to my MN successfully,but it takes about 20 minutes. What are the reasons?...
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"? Now,the CN(demo_cn_console in Linux platform) can link to my MN ,but it takes about 20 minutes. What are the reasons? thanks.
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"? Now,the CN(demo_cn_console in Linux platform) can link to my MN ,but it takes about 20 minutes. What are the resons? thanks.
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"? Now,the CN(demo_cn_console in Linux platform) can linke to my MN ,but it takes about 20 minutes. What are the resons? thanks.
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"? Now,the CN(demo_cn_console in Linux platform) can linked to my MN ,but it takes about 20 minutes. What are the resons? thanks.
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) triggered in "Zynq Hybrid design"? Now,the demo_cn_console can linked to my MN ,but it takes about 20 minutes. What are the resons? thanks.
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) be triggered in "Zynq Hybrid design"? Now,the demo_cn_console can linked to my MN ,but it takes about 20 minutes. What are the resons? thanks.
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wireshark.pcapng
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the wireshark screen shot is:
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the wireshark screen shot is:
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the wireshark screen shot is:
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Hello Powerlink-team Kalycito , I implement "Zynq Hybrid Design" on my zynq board, but "openMAC" IP is instead with "Axi Ethernet IP + Axi Dma IP" ,so i do not know how to trigger the #61 interruption (from openMAC IP to Ps7 ) in the application program. Can you tell me when is the #61 interruption (from openMAC to PS7) be triggered in "Zynq Hybrid design"? Now,the demo_cn_console can linked to my MN ,but it takes about 20 minutes.
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attachment is the source code of hrestimer-zynqtmr.c
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Hi,Powerlink-team Kalycito , I wrote a hrestimer-zynqtmr.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c. In hrestimer-zynqttc.c,there is a marco define: #define TTC_RESOLUTION_FACTOR 2304 ,and what is the value of TTC_RESOLUTION_FACTOR in my hrestimer-zynqtmr.c? and How to calculate it? the clock linked to the AXI timer is 100HMZ. thanks.
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Hi,Powerlink-team Kalycito , I wrote a hrestimer-zynqtmr.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c. In hrestimer-zynqttc.c,there is a marco define: #define TTC_RESOLUTION_FACTOR 2304 , and what is the value of TTC_RESOLUTION_FACTOR in my hrestimer-zynqtmr.c? and How to calculate it? the clock linked to the AXI timer is 100HMZ. thanks.
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Hi,Powerlink-team Kalycito , I wrote a hrestimer-zynqtmr.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c. In hrestimer-zynqttc.c,there is #define TTC_RESOLUTION_FACTOR 2304 , and what is the value of TTC_RESOLUTION_FACTOR in my hrestimer-zynqtmr.c? and How to calculate it? the clock linked to the AXI timer is 100HMZ. thanks.
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this is the content of my hrestimer-zynqtmr.c: +++++++++++++++++++++++++++++++++++++++++
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this is the content of my hrestimer-zynqtmr.c: +++++++++++++++++++++++++++++++++++++++++ include <common oplkinc.h=""></common> include <kernel hrestimer.h=""></kernel> include "xparameters.h" include "xtmrctr.h" //#include "xtmrctr_l.h" include "xil_exception.h" ifdef XPAR_INTC_0_DEVICE_ID include "xintc.h" //#include "xintc_l.h" include <stdio.h></stdio.h> else include "xscugic.h" include "xil_printf.h" endif include "xgpio.h" define TMRCTR_0_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID define TMRCTR_0_INTERRUPT_ID...
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Hi,Powerlink-team Kalycito , I wrote a hrestimer-zynqtmr.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c. In hrestimer-zynqttc.c,there is # #define TTC_RESOLUTION_FACTOR 2304 , and what is the value of TTC_RESOLUTION_FACTOR in my hrestimer-zynqtmr.c? and How to calculate it? the clock linked to the AXI timer is 100HMZ. thanks.
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this is the content of my hrestimer-zynqtmr.c: +++++++++++++++++++++++++++++++++++++++++ include <common oplkinc.h=""></common> include <kernel hrestimer.h=""></kernel> include "xparameters.h" include "xtmrctr.h" //#include "xtmrctr_l.h" include "xil_exception.h" ifdef XPAR_INTC_0_DEVICE_ID include "xintc.h" //#include "xintc_l.h" include <stdio.h></stdio.h> else include "xscugic.h" include "xil_printf.h" endif include "xgpio.h" define TMRCTR_0_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID define TMRCTR_0_INTERRUPT_ID...
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hrestimer-zynqtmr.c +++++++++++++++++++++++++++++++++++++++++ include <common oplkinc.h=""></common> include <kernel hrestimer.h=""></kernel> include "xparameters.h" include "xtmrctr.h" //#include "xtmrctr_l.h" include "xil_exception.h" ifdef XPAR_INTC_0_DEVICE_ID include "xintc.h" //#include "xintc_l.h" include <stdio.h></stdio.h> else include "xscugic.h" include "xil_printf.h" endif include "xgpio.h" define TMRCTR_0_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID define TMRCTR_0_INTERRUPT_ID XPAR_INTC_0_TMRCTR_0_VEC_ID...
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the source code of hrestimer-zynqtmr.c
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Hi,Powerlink-team Kalycito , I wrote a hrestimer-zynqtmr.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c. In hrestimer-zynqttc.c,there is define TTC_RESOLUTION_FACTOR 2304 , and what is the value of TTC_RESOLUTION_FACTOR in my hrestimer-zynqtmr.c? and How to calculate it? the clock linked to the AXI timer is 100HMZ. thanks.
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HI,Powerlink-team Kalycito circular buffer
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HI,Powerlink-team Kalycito
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Hi,Powerlink-team Kalycito , 1, I can not understand the circbuf up to this day，Would you please explain the role of it and offer me some diagram to indicate the data structure and the shape and location in the DDR memory? 2,What are the differences between the Common Memory and Shared Memory? thanks, Liu zhi qiang 8/30/2018
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Hi,Powerlink-team Kalycito , 1, I can not understand the circbuf up to this day，Would you please explain the role of it and offer me some diagram to indicate the data structure and the shape and locationin the DDR memory? 2,What are the differences between the Common Memory and Shared Memory? thanks, Liu zhi qiang 8/30/2018
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Hi,Powerlink-team Kalycito , 1, I can not understand the circbuf up to this day，Can you offer the diagram to indicate the data structure and the shape and locationin the DDR memory? 2,What are the differences between the Common Memory and Shared Memory? thanks, Liu zhi qiang 8/30/2018
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Hi,Powerlink-team Kalycito , 1, I can not understand the circbuf up to this day，Can you offer the diagram to indicate the data structure and the shape and location in the DDR memory? 2,What are the differences between the Common Memory and Shared Memory? thanks, Liu zhi qiang 8/30/2018
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my mnobd.cdc:
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picture3:
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picture2:
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picture1:
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Why the state of the CN1 is "NmtCsPreOperational2" all along? as the pictures
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 interruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core ought to occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 interruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (PS7)" occurs so frequently that all other programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (PS7)" occurs so frequently that all programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (PS7)" occurs so frequently that all programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. I connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0] pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (PS7)" occurs so frequently that all programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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Hello Powerlink-team Kalycito , thanks for your kindly reply. i connected the "interrupt" pin in "Axi Ethernt IP core" to "F2P[0:0} pin in "ZYNQ IP core", but the #61 intrruption in "ARM0 (Ps7)" occurs so frequently that all programs are blocked seemingly. so i wonder when does the #61 interruption in the ARM0 core occur? after received every "PRES" packet from a CN in a cycle period? after sent the last "PREQ" packet to a CN in a cycle period? thanks liu zhi qiang 8/25/2018
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make corrections: not #61 but #91 (XPAR_FABRIC_AXI_OPENMAC_0_TIMER_PULSE_IRQ_INTR)
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make corrections: not #61 but #91 (0X61) XPAR_FABRIC_AXI_OPENMAC_0_TIMER_PULSE_IRQ_INTR
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Hello Powerlink-team Kalycito , I implement Zynq HyBrid Design on my zynq board, but use "Axi Ethernet + Axi Dma" to instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
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the wire was linked as this diagram in system.bd
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Hello Powerlink-team Kalycito , I implement Zynq HyBrid Design on my zynq board, but use "emacps MAC" to instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
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the wire was linked as this in system.bd
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system.bd
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Hello Powerlink-team Kalycito , I implement Zynq HyBrid Design on my zynq board, but use "emacps MAC" instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
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Hello Powerlink-team Kalycito , I implement Zynq HyBrid Design on my zynq board, but use "emacps MAC" instead of "openMAC", so i do not know how to trigger the #61 interruption (from openMAC to zynq ),can you help me sir?
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https://max.book118.com/html/2017/0608/112591212.shtm
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https://max.book118.com/html/2017/0608/112591212.shtm
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hi Powerlink-Team-Kalycito, In Zynq Hybrid design, demo_mn_console (USER SPACE of STACK) run on arm cpu,and PCP (KERNEL of STACK) run on Microblaze, and exchange the DATA (.i.e network package,NMT command) through the SHARED MEMORY. I notice that they exchange the data via the F2P interrupt from PL to PS(the codes are below),could you please a little amply tell me what timestamp the interruption occurs in the per POWERLINK CYCLE (see the attachment picture )? SoC?PReq?PRes?SoA?ASnd? thanks liu zhi...
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hi Powerlink-Team-Kalycito, In Zynq Hybrid design, demo_mn_console (USER SPACE of STACK) run on arm cpu,and PCP (KERNEL of STACK) run on Microblaze, and exchange the DATA (.i.e network package,NMT command) through the SHARED MEMORY. I notice that they exchange the data via the F2P interrupt from PL to PS(the codes are below),could you please alittle amply tell me what timestamp the interruption occurs in the POWERLINK CYCLE (see the attachment picture )? SoC?PReq?PRes?SoA?ASnd? +++++++++++++++++++++++++++++++++++++++++++++++++...
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hi Powerlink-Team-Kalycito, In Zynq Hybrid design, demo_mn_console (USER SPACE of STACK) run on arm cpu,and PCP (KERNEL of STACK) run on Microblaze, and exchange the DATA (.i.e network package,NMT command) through the SHARED MEMORY. I notice that they exchange the data via the F2P interrupt from PL to PS(the codes are below),could you please alittle amply tell me what timestamp the interruption occurs in the POWERLINK CYCLE (see the attachment picture )? SoC?PReq?PRes?SoA?ASnd? +++++++++++++++++++++++++++++++++++++++++++++++++...
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to :Powerlink-team Kalycito during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount()", What is the reason for this issue? ========================= my Macro defines that related to dualprocshm are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000 thanks liu zhi qiang
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to :Powerlink-team Kalycito during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount()", What is the reason for this issue? ========================= my Macro defines that related to dualprocshm are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000
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to :Powerlink-team Kalycito during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", What is the reason for this issue? ========================= my Macro defines that related to dualprocshm are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000
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in the topic (https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/43ae9c65/) posted by Hassen G - 2017-12-04, Powerlink-team Kalycito said: ++++++++++++++++++++++++++++++++++++++++++++++ Powerlink-team Kalycito - 2018-05-30 Hi Hassen, For your first question: Regarding memory segment, common memory is used for exchanging control and information. Shared memory is used for bulk data exchange. For your second question: openPOWERLINK daemon application is running on Microblaze and it gets...
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in the topic (https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/43ae9c65/) posted by Hassen G - 2017-12-04, Powerlink-team Kalycito said: ++++++++++++++++++++++++++++++++++++++++++++++ Powerlink-team Kalycito - 2018-05-30 Hi Hassen, For your first question: Regarding memory segment, common memory is used for exchanging control and information. Shared memory is used for bulk data exchange. For your second question: openPOWERLINK daemon application is running on Microblaze and it gets...
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in the topic (https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/43ae9c65/) posted by Hassen G - 2017-12-04, Powerlink-team Kalycito said: ++++++++++++++++++++++++++++++++++++++++++++++ Powerlink-team Kalycito - 2018-05-30 Hi Hassen, For your first question: Regarding memory segment, common memory is used for exchanging control and information. Shared memory is used for bulk data exchange. For your second question: openPOWERLINK daemon application is running on Microblaze and it gets...
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in the topic (https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/43ae9c65/ ) posted by Hassen G - 2017-12-04, Powerlink-team Kalycito said: ++++++++++++++++++++++++++++++++++++++++++++++ Powerlink-team Kalycito - 2018-05-30 Hi Hassen, For your first question: Regarding memory segment, common memory is used for exchanging control and information. Shared memory is used for bulk data exchange. For your second question: openPOWERLINK daemon application is running on Microblaze and it gets...
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in the topic (https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/43ae9c65/ ) posted by Hassen G - 2017-12-04, Powerlink-team Kalycito said: ++++++++++++++++++++++++++++++++++++++++++++++ Powerlink-team Kalycito - 2018-05-30 Hi Hassen, For your first question: Regarding memory segment, common memory is used for exchanging control and information. Shared memory is used for bulk data exchange. For your second question: openPOWERLINK daemon application is running on Microblaze and it gets...
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I imitate the "zynq Hybrid design" scheme, use "dual processor+shared memory",but instead of openMAC IP with EmacPs and NO OS platform (bare-metal),the demo_mn_embedded run on CPU0 and Kernel stack part run on CPU1 . during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", the Macro defines are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define...
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screen shoting
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What really puzzles me is the demo_mn_embedded always printf "Kernel stack has gone,exiting..." because the ctrlk_process() function in daemon.c running on the CPU1 always Enter the dead cycle,so the ctrlk_updateHeartbeat() function does not run. ++++++++++++++++++++++++++++++++++ drivers/xilinx-zynqarm/drv_daemon/daemon.c ..... static void backgroundProcess(void) { BOOL fExit = FALSE; while (1) { ctrlk_updateHeartbeat(); fExit =** ctrlk_process()**; if (fExit != FALSE) break; } } ++++++++++++++++++++++++++++++++...
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I imitate the "zynq Hybrid design" scheme, use "dual processor+shared memory",but instead of openMAC IP with EmacPs,and demo_mn_embedded run on CPU0 and Kernel stack part run on CPU1 .during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", the Macro defines are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000 attachment...
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I am using the "zynq Hybrid design" scheme,but instead of openMAC IP with EmacPs,and demo_mn_embedded run on CPU0 and Kernel stack part run on CPU1 .during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", the Macro defines are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000 attachment file is my emacps drivers. What's...
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I am using the "zynq Hybrid design" scheme,but instead of openMAC IP with EmacPs.during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", the Macro defines are : /#define COMMON__MEM_BASE 0x2c000000 /#define SHARED_MEM_SPAN 0x10000000 /#define SHARED_MEM_BASE 0x30000000 attachment file is my emacps drivers. What's the cause of this issue? thanks
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I am using the "zynq Hybrid design" scheme,but insteadof openMAC IP with EmacPs.during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", What's the cause of this issue? thanks
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during powerlink MN running,a issue occurs:"assertion "pInstance_p != ((void*)0)" failed : file "stack/src/common/circbuf/circbuffer.c", line 607,function circbuf_getDataCount", Whatundefineds the cause of this issue? thanks
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstancel.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler of...
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstancel.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler of...
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstancel.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler of...
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstancel.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler of...
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstancel.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler of...
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1,I wrote my hrestimer-zynqttc-noos.c in imitation of stack/src/kernel/timer/hrestimer-zynqttc.c, in hrestimer_init() ,the TTC1/channel #0 and TTC1/channel #1 are be initialized to be used as two hrestimer,i did it same. is it correct? 2,I wrote my edrv-emacps-noos.c in imitation of stack/src/kernel/edrv/edrv-emacps.c, in edrvIrqHandler() function in file edrv-emacps.c, i found the code (line 768 and line 838) : ... edrvInstance_l.initParam.pfnRxHandler(&rxBuffer); ... and ... // Call Tx handler...
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Who can give a detailed manuals to dualprocshm library which is used for communication between the ARM core and the microblaze soft-ip processor ?Is there need two timer interruptions to run separately on ARM core and Microblaze core processors?How does dualporcshm library manipulate the share memory? Can you give a memory-map diagrams?thanks
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Who can give a detailed manuals to dualprocshm library which is used for communication between the ARM core and the microblaze soft-ip processor ?Is there need two timer interruptions to run separately on ARM core and Microblaze core processors?How does dualporcshm library manipulate memory? Can you give a memory-map diagrams?thanks
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Who can give a detailed manuals to dualprocshm library which is used for communication between the ARM core and the microblaze soft-ip processor ?Is there need two timer interruptions to run separately on ARM core and Microblaze core processors?thanks
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Who can give a detailed manuals to dualprocshm library which is used for communication between the ARM core and the microblaze soft-ip processor ?Is there need two timer interruptions to run on ARM core and Microblaze core processors?
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I am porting POWERLINK on Zynq + EmacPs, cpu1 run daemon.c and cpu0 run demo_mn_embeddded,The screen prints are as follows, could anybody tell me What is the reason for such a mistake？ CPU0: sending the SEV to wake up CPU1 Initialization returned with "No error / function call successful" (0x0) CDC file size 951 openPOWERLINK embedded MN DEMO application Using openPOWERLINK stack: V2.6.2 NODEID=0xF0 Initializing openPOWERLINK stack... shmMagic=0xAB12 Kernel features: 0x0000000b Usable features: 0x0000000b...
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1,How to replace openMAC with EmacPs or Emac Lite in Zynq Hybrid design? 2,How many restimer have to be in Zynq Hybrid design? 3,What is the role of synctimer in POWERLINK stack? thanks a lot
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How to replace openMAC with EmacPs or Emac Lite in Zynq Hybrid design?
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What is the role of the openmacTimer module (openmacTimer-rtl-ea.vhd) in openMAC Ip? thanks
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1,What is the role of the Interrupt ID# 61 (from openMAC to Cortex-a9-0) in Zynq Hybrid design?view the picture below 2,When does openMAC send TIMER_PULSE_IRQ signal to Cortex-a9 to trigger F2P(#61) interruption? thanks a lot.
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What is the role of the Interrupt ID# 61 (from openMAC to Cortex-a9-0) in Zynq Hybrid design?view the picture below
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Why my MN do not transition into "Basic Ethernet Mode"? showed as the picture below
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