Activity for Yuwu Xiong
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Yuwu Xiong posted a comment on discussion ngspice-devel
@Fra I guess you meant CKTload(), not SMPload(), for device model evaluation.
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Hi, Francesco, I did a quick test of your patch on 27 sept, and it seems it works for the test case I contrived. I tested with branch CUSPICE+6-untested-b+ of latest ngspice from sf.net, with the following configure options: ../configure --with-x --with-readline=yes --enable-cuspice --enable-xgraph Attached contains: the test circuit log without patch: cuda kernel failure reports can be seen log with patch: no cuda kernel failure report anymore Since the circuit is not meaningful, the op analysis...
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Yesterday I asked a qeustion on scicomp.stackexchange.com regarding an idea to speed up Newton iteration in solving non-linear system of equations in general, since I am not sure if this is a viable idea and if it's studied/implemented already: Parallelizing Newton-method in solving non-linear systems. The answer from Thales indicates that the idea has some connection with more general optimization methods widely studied/used in AI field. This gives me more incentive to try to test the idea based...
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Thank you, Francesco!
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It seems that the array size of rhs[] is one more than the matrix size, as shown in NIreinit(); And CKTcircuit.CKTrhs[0] is usually set to 0.0 after calling SMPsolve(); Looking into SMPsolve(), it seems that spSolve() does not touch RHS[0]. What's the purpose of this extra element, and why it's set to 0.0 after SMPsolve()? Many thanks!
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Thank you, Francesco!
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Hi, Francesco, Thanks for your reply. I am new to circuit analysis, so my questions may seem too dumb... What you mean by "the voltage and current sources are NOT supported in all the variations which are supported in the single core environment"? Looking at the "splicelib/devices/" tree, I found that the following devices have a CUSPICE subdirectory, so I was assuming that these devices are supported in CUSPICE, namely: res, cap, ind, vsrc, isrc, and bsim4v7 mosfet. In my test circuit above, I have...
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Hi, Reading cuBSIM4v7load(), it seems that it creates two Cuda streams trying to utilize GPU capability. however, in the loop through all models, the stream index is increase by i++, but not follwed by i%=2... I made a simple test that creating 3 nmos models and use all 3 models in a simple circuit: .title simple MOSFET circuit .include "model1.pm" ; BSIM4v7 model `nmos1` .include "model2.pm" ; BSIM4v7 model `nmos2` .include "model3.pm" ; BSIM4v7 model `nmos3` v_input vin gnd 0.0 pulse(0 1 10m 10m...
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Hi, Reading cuBSIM4v7load(), it seems that it creates two Cuda streams trying to utilize GPU capability. however, in the loop through all models, the stream index is increase by i++, but not follwed by i%=2... I made a simple test that creating 3 nmos models and use all 3 models in a simple circuit: .title simple MOSFET circuit .include "model1.pm" ; BSIM4v7 model `nmos1` .include "model2.pm" ; BSIM4v7 model `nmos2` .include "model3.pm" ; BSIM4v7 model `nmos3` v_input vin gnd 0.0 pulse(0 1 10m 10m...
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Thanks for your replay, Marcel.
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Thanks for your answer, Marcel. I have drawn a simplified flowchart for NIiter(), in a hope to understanding the 6 INITF flags. So far it seems that the current 6 MODEINITxxx correspond to INITF values 1 to 6 as mentioned in Nagel's 1975 PhD thesis (Appendix A4.15~A4.21), and the iteration loop returns OK only when the mode is set to MODEINITFLOAT (INITF=1)...but the meaning of these are still not clear to me... I guess the flowcharts in the thesis may be a bit outdate as compared to the current...
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Hi, In the tests directory, there are many netlist file *.cir, but it seems there is no too much explanations for the netlist. Usually how one to study the test cases? For example, there is a \tests\general\mosmem.cir which contains 12 NMOS transistors, how can I draw the schematic diagrams from the netlist? I tried to manually draw those transisters and connect them, but without a understanding of the purpose of the circuit, the lines are tangled togeter quickly thus it's nearly impossible to finish...
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Thanks for your reply, Marcel. I must confess that I am not familiar with circuit simulation enough to understand your reply...actually there are several other questions in my mind related to this. For example, where is the exact place the initial conditions are set? I also noticed that during iterations, CKTmode also changes, but what those INITF modes stands for, why the mode changes? ... In any case, for now I think it's ok for me to treat it as a "trick"...apparently I need spend more time on...
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Hi, I am new to ngspice (and circuit simulation). I just tested the OP analysis of a simple linear circuit below: 1 R1 2 +---xxxxxxxx-----+ | 10 ohm | | x + - x 30V x R2 20 ohm - - x | x | | +----------------+ 0 With the following netlist: Simple circuit r1 1 2 10 r2 2 0 20 v 1 0 30 I was expecting that it will converge in two steps, because the solutions of the two steps will be identical (which is true as verified), but ngspice actually takes a 3rd step...inspecting the code, it seems that the...
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btw, i use udp port 8080. and from rdv server i see both clients are communicating...
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I am new to this...according to the manual, I made two clients (one from office,...
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