wild pie

no problem, i come back checking updates just now. no delay to me, thanks for help,

i'm using nasm 2.11.08

also, i'd appreciate if you can activate my account (wild.pie) on nasm.us, in case i have other questions. thank you,

well, i have existing code to manipulate 64-bit seg descriptors, but i don't have 32-bit protected mode code. the problem is cpu enforces flat memory in long mode. don't want to spend too much time on this, so i posted on stackoverflow and here's a response agreeing with my suspects: https://stackoverflow.com/questions/49721801/does-ebp2-reference-ds-or-ss-segment does this make sense? if i'm wrong, can you tell me why [ebp*2] is the same as [ebp+ebp}? thanks,

but why [ebp+edx] and [edx+ebp] are different? it takes some time to test this in a 32-bit or 64-bit mode, but doable. is there an easier way to verify this?

is this forum abandoned? tried to sign up on nasm.us forum, but cannot receive activation email. i had no problem signup here with same email. also, nasm generates [ebp, eiz] for [eiz, ebp] (optimization for shorter machine code, which i think is incorrect), but it generates different codes for [ebp, edx] and [edx, ebp], which is correct.

nasm generates optimized code for [eax*2]. it generates the code as [eax + eax] instead. i just noticed it also replaces [ebp*2] with [ebp + ebp]. in [ebp*2], ebp is the index register, not base register. so this form references DS segment. in [ebp + ebp], ebp is used as base register, so it references SS segment. is this a nasm bug or i missed something? IDM vol 1 page 3-21 "Table 3-5 Default Segment Selection Rules", memory reference uses SS by default if EBP is used as base register Any memory...

nasm generates optimized code for [eax*2]. it generates the code as [eax + eax] instead. i just noticed it also replaces [ebp*2] with [ebp + ebp]. in [ebp*2], ebp is the index register, not base register. so this form references DS segment. in [ebp + ebp], ebp is used as base register, so it references SS segment. is this a nasm bug or i missed something? IDM vol 1 page 3-21 "Table 3-5 Default Segment Selection Rules", memory reference uses SS by default if EBP is used as base register Any memory...