Steph

Many thanks for your reply! I have one follow-up question: Why isn't the entire RAM available on the ZC702 specified in the device tree i. e. 0x0 - 0x3FFF_FFFF? Would this make any difference? I will DM you for more specific quesions :). Best regards Steph

Hi, I have some questions regarding the RAM layout of the "openPOWERLINK MN on Zynq Hybrid design" (Xilinx ZC702). As far as my understanding goes, the use of the RAM is divided into 4 main regions. The address editor in Vivado shows that 512 MiB of ram is mapped onto the PCP (0x2000_0000 - 0x3FFF_FFFF). This region is further divided into "Common Memory" (0x2C00_0000 - 0x2FFF_FFFF) and "Shared Memory" (0x3000_0000 - 0x3FFF_FFFF) as can be seen in openPOWERLINK_V2-master/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/include/dualprocshm-mem.h....

Hi, I have some questions regarding the RAM layout of the "openPOWERLINK MN on Zynq Hybrid design" (Xilinx ZC702). As far as my understanding goes, the use of the RAM is divided into 4 main regions. The address editor in Vivado shows that 512 MiB of ram is mapped onto the PCP (0x2000_0000 - 0x3FFF_FFFF). This region is further divided into "Common Memory" (0x2C00_0000 - 0x2FFF_FFFF) and "Shared Memory" (0x3000_0000 - 0x3FFF_FFFF) as can be seen in openPOWERLINK_V2-master/hardware/boards/xilinx-z702/mn-dual-shmem-gpio/include/dualprocshm-mem.h....