Sean Cross

Hi, I'm working with a CPU core that implements only the 16-bit "compressed" instructions of RV32I. It's an interesting project, and the approach results in a CPU core that's as small as the SERV core but runs at ~1 ipc. This makes it an attractive target for custom silicon due to its extremely low transistor count. The non-compressed RV32I instructions are handled by trapping to microcode that emulates missing instructions (using RV32C). So it can execute normal RISC-V code, it's just a ~400 cycle...