Activity for Roberto Hexsel
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Roberto Hexsel committed [r106]
documentation update
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new hardware and sosftware support for keyboard...
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improvements to fpgs RAM and LCD controller
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assembly test file for LCD controller
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ALtera design files for LCD controller
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3rd fix to GHDL build script
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2nd fix to GHDL build script
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fix to GHDL build script
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better GHDL build procedure
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added LCD display test program
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simpler BUS protocol, added LCD display
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added Altera files
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fixed writable reg0
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timing fixes to ALU, peripherals
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fixed LL-SC, peripherals do not generate wait-s...
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fixed LL-SC, peripherals do not generate wait-s...
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fixed LL-SC, peripherals do not generate wait-s...
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bus interfaces are now fully synchronous (2)
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bus interfaces are now fully synchronous
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tb for checking pipeline
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fixed TRAPS (test file missing)
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fixed TRAPS
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timing improvements
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fixed lw r1, -> sw ,0(r1) stall
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fixed overflow exception (test files)
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fixed overflow exception
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fixed I/O address ranges
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removed all cache latency generics
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(fix to) added kbd-7seg Macnica peripherals
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added kbd-7seg Macnica peripherals
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added FPGA-friendly ROM
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added FPGA-friendly instruction cache plus asso...
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up to date test results
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replaced RAM model for synthesis
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replaced tri-state data bus by mux
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doTests.sh can now do timing-independent tests
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added functionality to display cache statistics
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update to UART driver (ii)
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update to UART driver
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changes to VHDL code preparing for synthesis (ii)
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changes to VHDL code preparing for synthesis
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improved documentation
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fixed uartrx.c
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fixed compilation scripts
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fixed UART's code
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fixed several bugs in the UART + driver
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fixed signal names in UART
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fixed counter test result
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updated UART software
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UART now generates interrupts
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remote UART now reads/writes from/to files or s...
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updated v.sav
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updated tb
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fix RAM wait states
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fix paths in doTests.sh
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fix addresses for added interrupt handlers
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added interrupt handlers
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counter interrupt and exceptiond handlers
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fixed entry point
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fixed cMIPS.s
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are things broken still?
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are things broken still?
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things are broken
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added missing test result for lwl_lwr
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added missing test result for lwl_lwr
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missing test result for lwl_lwr
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fixed error in wait states
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pushing out stale files
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update might went wrong - fixed
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update might have gone wrong
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added tests for LWL and LWR instructions
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added LWL and LWR instructions
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fixed eret, simulation aborts on unaligned refe...
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fixed eret, simulation aborts on unaligned refe...
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revised UART
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fixed fixed tests
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fixed tests
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fixed path setting in doTests.sh
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fixed: simulation aborts on invalid opcode
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added peripheral do dump RAM cntents plus docs
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added peripheral do dump RAM cntents
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upgrade to interrupt generator/counter
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small fixo do tb.pdf
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