zhouqing

I want to cnovert the schematic diagram to EDIF , do you know any sotfware can do that? Saul recommend yosys above, that a cool tool. but it have no function that implement the convertion. Is there any softwate that can do it and compatible with sosys and ngspice?

HI Robert thanks for reply. Now the gtkwave can work well. the reason is just you mentioned above. when load the signal, it should be clickt "append", then it display related waveform... I remember I click something previously after load the signal with gtkwave, maybe I just dont click the "append" button. thanks you very much.

hi Robert thanks for reply. according to your comment, I add lines to halfadder netlist file : eprvcd 1 2 30 40 > halfadder.vcd but when I run the command :gtkwave halfadder.vcd with the terminal, thereis nothing plotted in the gtkwave software. the halfadder.vcd file $date July 01, 2017 00:30:17 $end $version ngspice 26 $end $timescale 1 us $end $var wire 1 ! 1 $end $var wire 1 " 2 $end $var wire 1 # 30 $end $var wire 1 $ 40 $end $enddefinitions $end #0 $dumpvars 0! 0" 0# 0$ $end #1000000 1" #1000000...

Hi Holger, thanks for reply, here is another question, how to plot the waveform of results ? when add the line below to the netlist file .control plot 1 2 30 40 .endc its just plot four straight lines, parallet to x-axis, their y-axis value is 1 2 30 and 40 respectively, but not waveform. I dont know how to upload the image of result. how to plot that waveform?

Hi Saul thank you for recommand. that software is cool. but it seems cant convert the shcematic to edif file. Is there any software can do it ?

hi Holger thanks for reply when correct line from stimulus file 6 1s 0s now the result is right. but I still have something dont understand. first, the file ngspice\tests\xspice\digital\d_source.circ that you recommended Code Model Test: d_source * (compile (concat "SPICE_SCRIPTS=. ../../../src/ngspice " buffer-file-name) t) vdummy dummy 0 DC=0 a_source [a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab] d_source1 .model d_source1 d_source (input_file="d_source-stimulus.txt") .control set noaskquit set noacct tran...

OK , I've reedit it. It looks better. can you tell me whats the problem of my netlist file and related input file?

hi all I write a halfadder netlsit and related inputfile, when load it with ngspice , there is some errors halfadder netlist: ----- halfadder test : and, xor, d_source *** analysis type*** vdummy dummy 0 DC=0 a_source [1 2] d_source1 .model d_source1 d_source (input_file="halfadder-stimulus.txt") *** and block*** a1 [1 2] 30 d_and1 .model d_and1 d_and (rise_delay=1.0e-6 fall_delay=2.0e-6 + input_load=1.0e-12) *** xor block*** a2[1 2] 40 d_xor1 .model d_xor1 d_xor (rise_delay=1.0e-6 fall_delay=2.0e-6...