Nikolaus Schweyer

Hi, I am new in LogiSim and wanted to simulate a small circuit shown in the attachment as png. The counter CntEqu shall count how many consecutively equal data are input from ROM. The counter value together with the 4bit data is output with register RegOut. The D-Flipflop FFL shall flag if new data are available. In simulation of this circuit I found two errors. I used Logisim Windows 2.7.1. Error 1: The counter CntEqu is missing the first count. The synchronous 4bit counter 74161 has two enable...