Matt Venn

Thanks Giles! that answered all my questions.

Hi, I've just been experimenting with the verilator support -very nice! I have a few questions - the inputs and outputs set in the [ ], they are just listed in order defined in the verilog? And buses are broken into individual nets? What is the ~ symbol for in the example: [Sample Valid ~d5 ~d4 ~d3 ~d2 ~d1 ~d0] How does the system know what voltage is coming out on the outputs? When I first started playing it seemed it was 1v, but later when I checked again it had changed to 3v (my PSU voltage)....

fixed examples for opencv 2.4.8

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