Activity for Luca Longinotti
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Luca Longinotti modified a wiki page
jAER USB Driver Install
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jAER discussions moved to Google Groups
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The SourceForge discussion forums are moving to Google Groups. Read our announcement here: https://sourceforge.net/p/jaer/news/2017/09/jaer-discussions-moved-to-google-groups/ Subscription is open to everyone. We encourage you to subscribe to all lists that apply to you!
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After moving all our code to GitHub, it became necessary to find a good replacement for the SourceForge discussion forums. To also support easy e-mail announcements, as well as a good mailing-list and web-interface integration, we decided to use Google Groups. The following new groups are available: https://groups.google.com/d/forum/jaer-users https://groups.google.com/d/forum/caer-users https://groups.google.com/d/forum/davis-users https://groups.google.com/d/forum/dynapse-users This covers all...
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jAER discussions moved to Google Groups
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I don't have any experience in implementing UART at such a low level, usually any kind of microcontroller or OS has libraries for that, and for FPGAs you have modules by the vendor or talk to some external chip over a parallel bus. Xilinx for example has IP cores to do this: https://www.xilinx.com/products/intellectual-property/1-4c5ro4.html According to https://en.wikipedia.org/wiki/RS-232#RTS.2C_CTS.2C_and_RTR the meaning of RTS/CTS changes depending on half or full-duplex communication, modern...
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Hello, indeed if sending commands works, then also the command to enable events should have worked. And it probably did. UART0 is a slave port, so it will start trying to send bytes right away, and you need to read the data and do the flow-control yourself. So you wouldn't control CTS, the eDVS does that when it's ready to receive data (commands in your case), and you'd assert RTS to signal you are ready to get the data. I hope this helps, have a nice week-end!
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jAER migrated to GitHub
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Pasting answers from me from a private e-mail discussion where we solved this: If you indeed want to work only via the connectors and do the biasing yourself, there is no official documentation concerning this, as we do not support this mode of operation currently. The documentation you can find is the code, look at the firmware that does biasing and figure out how to replicate that in your system: https://github.com/inilabs/devices/blob/master/firmware/CypressFX2/SeeBetterLogic_DAVIS/main.c BiasWrite()...
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Hello, first of all sorry for my late reply, I was away on vacation and just returned today. The controls are present since some time (2016?) also in jAER, under "Hardware Configuration" -> "External Input" tab. So cAER and jAER can both control this. The graphic that shows the bits may not be the clearest way to look at events, especially as it includes the timestamp in the bit count. When you're loading things in Matlab or looking at files, you always have 32bit data and 32bit timestamp. The part...
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cAER has the file output module that can do this in AEDAT 3.1 format (-DENABLE_FILE_OUTPUT=1).
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caerDeviceConfigSet(deviceHandle, DAVIS_CONFIG_MUX, DAVIS_CONFIG_MUX_TIMESTAMP_RESET, 1);
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There is also https://github.com/simbamford/AedatTools which is a more generic and advanced set of scripts, supports caer data files too.
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The jAER Subversion repository has moved to GitHub. Read our announcement here: https://sourceforge.net/p/jaer/news/2017/05/jaer-migrated-to-github/
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Tobi already explained how jAER works and what parts to look at, though for what you want to do, just get data from the camera and send it off to a PCI-Express FPGA, I'd highly recommend using libcaer instead. It's a minimal C library that simply sets the camera up and gives you back the events in a simple, efficient in-memory format that you can then send to your device. It's also got a C++ interface if you prefer that.
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The values are in microseconds, relative to the last wraparound. 15 bits are used for timestamps, so ~32ms between wrap-arounds. What do you mean by set the clock? The timestamps will always be 1µs, changing that requires massive changes in the whole stack, from logic to software. You can reset them to zero (TimestampReset in cAER, pressing '0' in jAER). You can also synchronize the camera to anything that outputs a 10 KHz clock, or use the camera as a source for such clock, see https://inilabs.com/support/hardware/synchronisation/...
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Yes, the AEDAT 2.0 file format is not equal to the USB one. It's the most similar one as I've said, but it's far from equal. Lots of things that come via USB are not forwarded to file as they only exist to help interpret the USB stream, which is 2 bytes wide, while the file is made up of 8 bytes wide events (4 byte timestamp + 4 byte data). See https://inilabs.com/support/software/fileformat/#h.4ydb2xpu03ik for details on the file formats.
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I've updated the news post at https://sourceforge.net/p/jaer/news/2017/05/jaer-migrated-to-github/ to also mention this information.
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jAER migrated to GitHub
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jAER migrated to GitHub
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It's certainly possible to do this, but the idea of libcaer is only to be minimal device access. For file formats, reading and writing, there is cAER (and jAER to a certain extent). If what you want is to open an AEDAT 2.0 file, you can indeed mostly reuse the existing code, as AEDAT 2.0 is a more or less straight dump of the USB events as they come, with different encoding, and not all of them are preserved, but it is slightly easier to parse than AEDAT 3.X, which offers more advanced features.
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Hi, yes that looks like you had an out-of-date jAER. Both jAER in SVN (old) and GitHub (new) should have the changes needed, and an up-to-date dist/jaer.jar has been committed to both. But you should use the GitHub version from now on, as that's where all development will be going on. I see you opened a bug on GitHub inilabs/devices but closed it right after, so I assume you solved your problem. Can you confirm updating jAER was the solution? Or something else? Thanks and have a nice day, Luca.
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jAER migrated to GitHub
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Test commits.
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jAER: update JAR.
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SystemLogic2: MachXO: update Changelog.
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SystemLogic2 ECP3 DAVIS: new binaries.
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jAER: update DAVIS config/hardware-interface to use new logic revision 9980.
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SystemLogic2: APS: update comments to reflect new sizes. Update D4A config records to be aligned with new
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SystemLogic2 MachXO3 346: new binary file.
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SystemLogic2: new DAVIS240 releases.
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SystemLogic2: remove AERCorrFilter binary, unmaintained.
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SystemLogic2: DAVIS: update all logic versions.
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SystemLogic2: FX2/3 SM: remove last multiplier, replace with fully expanded register.
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SystemLogic2: APS: small fixes, naming, ADCTestMode only works with internal ADCs, QuadROI Info needs only be
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SystemLogic2: reduce size of counters to conserve resources.
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SystemLogic2: APS: remove second sync reg, uses too much ressources.
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SystemLogic2: APS/IMU SPI Config: don't generate some configs if the content is zero, that's the default
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SystemLogic2 APS SM: add one more sync register, because we're doing an enable on the last register and that might make things more prone to failure.
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SystemLogic2 TimestampGenerator: fix for DAVIS240 boards, they use a MachXO, not a MachXO2.
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PatchMatchFlow: fix self-assignment. This is not the first time I fix this. Either it's a useless line of code and should not be there, or it is an error and should be fixed.
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jAER: update Java requirement to 1.8 in Eclipse, some code uses new features.
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Hi, that setting applies only to our bigger FPGA-based dev-kit devices. The DAVIS240C has no filters onboard, the small CPLD we use there has no spare ressources. jAER doesn't query device capabilities in its GUI, so always displays that field, even if it can't be used. Hope this helps, have a good day, Luca.
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Please direct questions about the ROS dvs support to the developers of said support at https://github.com/uzh-rpg/rpg_dvs_ros/issues Thanks!
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Hi, yes it is active-low, but the normal DVS state machine already drives it so that it is always disabled (not in reset), when you enable external AER control, so you don't have to care about it.
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The simples AER state machine we have is this: https://sourceforge.net/p/jaer/code/HEAD/tree/devices/logic/SystemLogic2/common-source/GenericAERStateMachine.vhd In principle it's a 4-phase handshake with a few extra features such as delays. An easy test to do on your side is to just redirect REQ to ACK directly and look at the pins with an oscilloscope, you should see the frequency of rising edges correlate with more or less activity in front of the camera. At least that way you know the camera and...
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Hi, was the DAVIS240C camera setup correctly? Even when you take over the DVS bus, the whole camera needs to be setup and biased correctly via USB. Also, the normal DVS state machine needs to be disabled, and the external AER control setting enabled. You can do this via jAER or cAER.
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jAER: fix assignment of sadValue to itself.
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jAER bias settings: ensure all default bias set...
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Yes, timestamps should increase, as packets get generated by slicing time (ie. one...
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This has been fixed in SVN. The problem was wrong biases in the DAVIS128 bias XML...
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DAVIS128: disable color correction and auto-WB.
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DAVIS128: try clean biases.
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Please don't change the input/output modules. These are intended for generic event...
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jAER: update jAER.jar.
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StreamTester: update Lattice Diamond 3.9 projec...
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Hi Garrick, to convert from jAER XML to cAER/libcaer format, you are correct that...
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Hi Garrick, to convert from jAER XML to cAER/libcaer format, you are correct that...
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SystemLogic2: update all references (but Cochle...
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I don't think the RPG people go through Matlab for that, at least for their ROS implementation...
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Firmware/Logic: delete old DAVIS_FX2V4, delete ...
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Yes, this is correct. Timestamp reset is sent as a separate packet with only itself,...
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Hi. I'm not sure what you're trying to do here. Starting/stopping logging means you're...
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jAER: add biases for Davis346mini.
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jAER: fix dead code in PatchMatchFlow again. Fi...
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jAER: new chip class for Davis346mini camera.
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jAER: PatchMatchFlow: fix dead code at end (|| ...
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SystemLogic2: MachXO3: add registers to InvenSe...
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jAER: DAVIS FX3: support IMU orientation.
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SystemLogic2: IMU: add support for specifying I...
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MachXO3 logic: change orientation of APS/DVS fo...
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This should be fixed now. If not, please update ticket #35 on GitHub. https://gi...
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MachXO3 logic: update 346 bitstream. Remove 640...
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MachXO3 logic: remove LED3, will not be on prod...
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SystemLogic2: update all ECP3 DAVIS binaries.
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jAER: revert timestamp-correction code. Now is ...
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MachXO3 logic: fully remove external ADC ports ...
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SystemLogic2: ChipBias Config: add one more reg...
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MachXO3 logic: reduce resource usage.
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SystemLogic2: update revision number for ECP3/M...
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MachXO3 logic: change module address for microp...
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SystemLogic2: DAVIS346 logic: enable pixel filt...
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SystemLogic2: APS ADC SM: define ROI Regions 1/...
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SystemLogic2: APS ADC SM: if the board has no e...
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SystemLogic2: TimestampGenerator: fix clock cor...
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FX3 fw: update binaries.
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FX3 fw: remove ExternalADC info load, not used ...
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SystemLogic2 DAVIS346: updated bitstream.
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SystemLogic2: fix timestamp drift due to FX3 cl...
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SystemLogic2: fix usages of Multiplexer to take...
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SystemLogic2 MachXO3: update project file with ...
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SystemLogic2 MachXO3: add full support for Inve...
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FX2 SeeBetterLogic: add comments to XSVFPlayer ...
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Spartan6 logic: update flash MCS files. Remove ...
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jAER: classpath: fix svn:mime-type property.
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jAER: classpath: fix relative path to matlabcon...
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SystemLogic2 FX3: update all constraint files w...
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StreamTester MachXO3: update clock frequencies ...
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StreamTester ECP3: working binary for SATA test...
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FX3 SATA support: now working!
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