John Wehle

Adding a small delay to the case statement does produce the desired results. I'll see about taking up the gtkwave issue over with the gtkwave people. Thanks for your time and your guidance. -- John

It would be useful if the perceived glitch on clk_1_5 was visible in gtkwave. The circuit is intended to be implemented by a FPGA whose combination logic block is guarenteed not to glitch if certain critiera is meet. This fact is being leveraged by the technical note I mentioned in how they implemented the divider. Making the change you suggested to using a default clause in the case block does eliminate one of the glitches perceived by the simulator. Do you have a suggestion on how to let the simulator...

possible false clocking

Here's the patch.

mpd-5.8 patch for l2tp self_port