I think it is OK to close this as it will be difficult to implement it and there is already a nice way to solve it using the shortcuts of StevenAZ. Thanks
For those that want to solve this problem now. You can install in eclipse the plugin GLANCE. http://www.exyte.com/glance/updates This allows you to search and highlight multiple occurrences on any file. Better than nothing.
Sorry again my bad!. The code had a typo. Please ignore this ticket again.
Highlight and format problem with defines
Sorry i close this ticket. The error was that i was calling wrong the command release for Questa flavor. It should be task force_wrp_tdc_data(logic [9:0] value); `ifdef VCS $hdl_xmr_force("secure_core_tb_top.u_secure_core_wrp.secure_core_top_1.U00.U05.U02.TDC_XB", "value", "0 ps", "freeze", , 0); `else //QUESTA force secure_core_tb_top.u_secure_core_wrp.secure_core_top_1.U00.U05.U02.TDC_XB = value;//direct force DUT intern signal `endif endtask task release_wrp_tdc_data; `ifdef VCS $hdl_xmr_release("secure_core_tb_top.u_secure_core_wrp.secure_core_top_1.U00.U05.U02.TDC_XB",...
Wrong error in SVeditor code parser with tasks inside interfaces
Dear Synath, yes that works. Is really not possible to write the "=" in the macro. It is strange that the compilers and the simulators accept that. SVEditor could change the error to a warning :D
Maybe, there is a workaround or other way to write this using less parenthesis.
Synxtax checker problem with property
Wrong begin 2 end selection using ALT+SHIFT+Upperarrow
Thanks!, both shortcuts are very useful for large blocks. The problem is that i tend to forget those nice shortcuts. Anyway, it would be also nice to highlight begin/end in both editor panes. I think supporting that way is also intuitive and it does not require to do anything / remember the shortcut.
matching braces for begin end
Usage of define macros in an assignment returns a false error
I think we can close this. This has been solved with the last versions of SVEditor. I don´t know which version exactly solved the problem, but now it works.
Wrong error message from SVEditor with cross construct
Add multiple occurrence feature in VHDL editor mode
I add a new case 3) usage of with inside a cross coverage cross_keycontrol_destination_keynumber: cross cvp_keycontrol_first_value_sequence, cvp_keycontrol_status_key_destination, cvp_keycontrol_status_key_number { ignore_bins IGNORED_keycontrol_3rdbit2one_in_case_of_key_number0_2 = ((binsof(cvp_keycontrol_first_value_sequence) with (cvp_keycontrol_first_value_sequence>3))&& ( binsof(cvp_keycontrol_status_key_number) with ((cvp_keycontrol_status_key_number==0)||(cvp_keycontrol_status_key_number==2)))...
SVEditor code parser general problems
SVEditor code parser has problems with soft constraints
Hi, It is true. On the new 2.0.7 i couldn´t reproduce. Please, close the ticket. Maybe it was my mistake. Sorry! Best regards, Jonathan
Bad formating for class end label
Wrong indentation using DPI keywords
Wrong indentation using end label for covergroups
Format /beautifier of new feature matching begin/end code is not working with some cases, besides it is broken in 2.0.1
Sorry it was my fault. Please close this ticket. It is not true what i stated and it is working.
Wrong format using fork declaration
Format /beautifier of special code in systemverilog is wrong
By the way, if you can support/save different color profiles would be also good :) Thanks
Support change of matching bracket color in SVeditor - eclipse
I realized that in .f file i had also included a .txt file, could it be that the...
UVM_MACROS not recognized even if included in .f file
Dear SVEditor developers, Sorry for the late answer. I was sick. I have tried Ctrl+A,...
Auto Block commenting closing hangs or it is too slow with big SV files
Another example in a second picture. This time after @(event_test);
SV format is not correct using ifdef after assert sv keyword
Wrong beautify/formatting in systemverilog constraint block