Activity for José María Casanova Crespo
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José María Casanova Crespo committed [e3ecf4]
v3d: Fix swizzle in DXT3 and DXT5 formats
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v3d: Include supported DXT formats to enable s3tc/dxt extensions
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vc4: Avoid negative scissor caused by no intersection
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vc4: Enable lower_umax and lower_umin
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nir/algebraic: optimize iand/ior of (n)eq zero when umax/umin not available
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vc4: enable lower_isign for VC4
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vc4: Add missing range_base/range at nir_load_ubos in yuv_blit fs.
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vc4: Add missing load_ubo set_align in yuv_blit fs.
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vc4: Enable nir_lower_io for uniforms
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broadcom: Fix implicit declaration of ffs for Android build
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v3d: Primitive Counts Feedback needs an extra 32-bit padding.
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meson: require valgrind 3.10.0 to enable it with freedreno
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glsl: fix typos in comments "transfor" -> "transform"
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glsl: TCS outputs can not be transform feedback candidates on GLES
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glsl: fix recording of variables for XFB in TCS shaders
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iris: setup EdgeFlag Vertex Element when needed.
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v3d: add shader-db stat to count SFU stalls
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v3d: Avoid scheduling an instruction that stalls waiting for SFU retval
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tgsi_to_nir: only update TGSI properties of the current shader stage
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mesa: reverse no_error on compressed_tex_sub_image for TEX_MODE_CURRENT
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mesa: recover target_check before get_current_tex_objects
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v3d: writes to magic registers aren't RF writes after THREND
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v3d: flag dirty state when binding compute states
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gallium: do not increase ref count of the new throttle fence
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v3d: request the kernel to flush caches when TMU is dirty
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broadcom: document known hardware issues for L2T flush command
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v3d: Add Compute Shader support
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v3d: trivial update to obsolete comment
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v3d: add new flag dirty TMU cache at v3d_compiler
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v3d: Explicitly expose OpenGL ES Shading Language 3.1
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intel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO
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intel/fs: shuffle_64bit_data_for_32bit_write is not used anymore
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intel/fs: shuffle_32bit_load_result_to_64bit_data is not used anymore
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intel/fs: Use shuffle_from_32bit_read for 64-bit FS load_input
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intel/fs: Remove old 16-bit shuffle/unshuffle functions
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intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function
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intel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read
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intel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load
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intel/fs: Use shuffle_from_32bit_read at VS load_input
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intel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES
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intel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD
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intel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read
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intel/fs: Use new shuffle_32bit_write for all 64-bit storage writes
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intel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo
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anv: finish the binding_table_pool on destroyDevice when use_softpin
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intel/compiler: relax brw_eu_validate for byte raw movs
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i965/fs: Enable store_ssbo for 8-bit types.
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i965: Support for 8-bit base types in helper functions
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spirv: Include headers and grammar for SPV_KHR_8bit_storage
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intel/fs: use uint type for per_slot_offset at GS
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i965/fs: Enable conversions to 8-bit integers
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intel/compiler: grf127 can not be dest when src and dest overlap in send
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i965/fs: Register allocator shoudn't use grf127 for sends dest
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anv: Enable SPV_KHR_8bit_storage and VK_KHR_8bit_storage
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spirv/nir: Add support for SPV_KHR_8bit_storage
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i965/fs: unspills shoudn't use grf127 as dest since Gen8+
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nir: Add support for 16-bit types (half float, int16 and uint16)
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spirv/nir: Add support for SPV_KHR_16bit_storage
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glsl: Add 16-bit types
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nir: Add rounding modes enum
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mesa/st: Handle 16-bit types at st_glsl_storage_type_size()
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nir: Handle fp16 rounding modes at nir_type_conversion_op
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spirv: Enable FPRoundingMode decorator to nir operations
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nir: Populate conversion opcodes to 16-bit types
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spirv/nir: Handle 16-bit types
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i965/vec4: Handle 16-bit types at type_size_xvec4
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i965: Support for 16-bit base types in helper functions
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i965/fs: Handle 32-bit to 16-bit conversions
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i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type
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i965: Add support for control register
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i965/fs: Define new shader opcode to set rounding modes
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i965/fs: Enable rounding mode on f2f16 ops
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i965/fs: Add remove_extra_rounding_modes optimization
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i965/fs: Add byte scattered write message and fs support
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i965/fs: Use byte_scattered_write on 16-bit store_ssbo
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i965/fs: Predicate byte scattered writes if needed
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i965/fs: Add byte scattered read message and fs support
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i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg
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i965/fs: Use byte scattered read for 16-bit load_ssbo
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i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit components
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i965/fs: Enables 16-bit load_ubo with sampler
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anv: Enable SPV_KHR_16bit_storage and VK_KHR_16bit_storage for SSBO/UBO
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i965/fs: Use untyped_surface_read for 16-bit load_ssbo
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i965/fs: retype offset_reg to UD at load_ssbo
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