Activity for Hassen G
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Hassen G posted a comment on discussion Getting Started
Hi Powerlink-Team-Kalycito, Thank you for your answer. I am trying to implement a design where the kernel part of stack runs in de2-115 using cn-single-hostif-drv design and an external MCU with ARM processor instead of Nios II (gpio) running user side of stack and connected to the kernel via hostinterface. I would like to know what should I reconfigure to be able to configure this external MCU and where may I find the configuration of the hostinterface pins the nios II gpio ( I checked the docs...
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Hello, I am trying to understand through hostinterface code and docs how it is connecting the kernel stack and user stack. How the cn_single_gpio_hostint send data ( guess pdo/sdo value) to pcp cn_single_drv_hostint ? As I read, cn gpio uses the parallel ip ( when needed) to communicate with the hostinterface, I would like to know : 1- Where the data sent from gpio is registered and how gpio informs pcp of new data ? 2- How the pcp passes information received from master ? Best regards, Hassen
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Hi Team Kalycito, Thank you for your fast reply.
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Hello, I want to implement this design http://openpowerlink.sourceforge.net/doc/2.7/2.7.1/page_platform_altera-cn.html I am really confused about which one to choose: 1-Altera DE2-115 https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=163&No=502&PartNo=1 2- Industrial Networking Kit (INK) https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=162&No=511 The second one is the Altera DE2-115 with INK but the first one has already two Gigabit Ethernet...
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Hello Team Kalycito, I update the design to vivado 2018.2 und I opened a pull request here Regards, Hassen
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Hello, Trying to adapt the MN zynq hybrid ( kernel oplk runs in Microblaze and the user oplk runs in Linux in Arm) design to work as a CN Hybrid design, I followed these steps: 1- Nothing changed in the hardware 2- In order to compile the kernel libraries: remove the module NMT and disable the high resolution timer (CONFIG_TIMER_USE_HIGHRES) add the HARDWARE_DRIVER_OPENMAC_CN_SOURCES and configure the cmake file to compile and generate the libraries necessary for the CN kernel side 3- Nothing changed...
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Hello, I want to ask if someone had successfully upgraded the design for Hybrid_Zynq MN to a new vivado version ? I want to upgrade it to vivado 2017.4 but I get some serious errors when trying to upgrade the openmac IP ! Regards, Hassen
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Hallo Powerlink-team Kalycito, I posted this topic also in Getting Started Forum and I answered there that it was a configuration issue with a jumper in the AVNET board. ( I could not delete this topic) https://sourceforge.net/p/openpowerlink/discussion/newbie/thread/e2188c38/#18cd Thanks, Hassen
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Hi Powerlink-Team-Kalycito, Thank you for your reply. I am working now on adapting this design as CN, so it would be helpful if you may share informations about the modifications that should take place in this design ( in which level, components ..) I may try to modify the design of the microblaze and let you know my progress. Best regards, Hassen
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Hi Powerlink-Team-Kalycito, Thank you for your reply. I am working now on adapting this desgin as CN, so it would be helpful if you may share informations about the modifications that should take place in this design ( in which level, components ..) I may try to modify the design of the microblaze and let you know my progress. Best regards, Hassen
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Hello, Trying to adapt the MN zynq hybrid ( kernel oplk runs in Microblaze and the user oplk runs in Linux in Arm) design to work as a CN Hybrid design, I followed these steps: 1- Nothing changed in the hardware 2- In order to compile the kernel libraries: remove the module NMT and disable the high resolution timer (CONFIG_TIMER_USE_HIGHRES) add the HARDWARE_DRIVER_OPENMAC_CN_SOURCES and configure the cmake file to compile and generate the libraries necessary for the CN kernel side 3- Nothing changed...
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Hi Team Kalycito, Thank you for the response. The CN fails at the start of the processSync to get the sync event from the shared memroy. I assume it is a configuration issue in the driver side of the linux to communicate with the PCP. It is odd but after like every 70-100 Cycle, the CN runs the timesyncucal_waitSyncEvent once successfully! tOplkError timesyncucal_waitSyncEvent(ULONG timeout_p) { int ret; **ret = ioctl(fd_l, PLK_CMD_TIMESYNC_SYNC, timeout_p);** if (ret == 0) return kErrorOk; return...
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Hi Team Kalycito, Thank you for the response. The CN fails at the start of the processSync to get the sync event from the shared memroy. I assume it is a configuration issue in the driver side of the linux to communicate with the PCP. It is odd but after like every 70-100 Cycle, the CN runs the timesyncucal_waitSyncEvent successfully! tOplkError timesyncucal_waitSyncEvent(ULONG timeout_p) { int ret; **ret = ioctl(fd_l, PLK_CMD_TIMESYNC_SYNC, timeout_p);** if (ret == 0) return kErrorOk; return kErrorGeneralError;...
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Hi Kalycito, Thank you for answer. I used the patch below to generate the library liboplkcnapp-kernelpcp.a required for the compiling of the demo_cn_console in "Kernel stack on Zynq PCP". I used the same module "oplkmnzynqintf.ko" generated in mn-demo and hardware configuration to run the Zynq hybrid as cn and the mn in PC The stack initialisation and PDO mapping is correctly executed: MN output in PC: 2018/01/22-17:49:00 EVENT HISTORY HistoryEntry: Type=0x3002 Code=0x8243 (0x01 00 00 00 6F AE 4A...
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Hello, As it mentioned e.g. for the Altera Nios II: there are the designs of cn and mn nodes with respectively the demo mn and cn embedded applications. There is not the design and/or stack library configuration for cn in hybrid design, so my question is: would it be the implementation of the cn on hybrid design and its stack configuration in the future. It would be nice to test e.g. the time required between Preq and Pres when the kernel side of the mn and cn is running on microblaze . Best regards,...
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Hi, I want to debug the application which is running on the microblaze, so I can better understand which parts of the stack is running in the mb, what kind of Interruptions are being triggered and why we have sahred and common memories. I posted these questions in another topic here . If anyone could give me some informations, it would be helpful. Best regards, Hassen
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Hello, You have to add new BSP and point it to the hardware file "hardware/lib/generic/microblaze/xilinx-z702/mn-dual-shmem-gpio/hw_platform/system.hdf" and then you add this bsp as a reference in your project in Project Properties -> Project References. After implementing the microblaze and trying to connect to it: I get this error "MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properlyUNABLE to STOP MicroBlaze" and because the mb works fine,...
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Hello, Going through the block design and the sources code of the hybrid example on Zynq to better understand it, I have some questions and I hope anyone can help me : 1) What is the role of the shared and common memories which are parts of the DDR memory ? 2) What is the application that is running in Microblaze ? it it getting the value of the PDO from a memory and send it when receiving Preq ? and where can I found the source code ? 3) After receiving a frame, the openmac will activate an interrupt...
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Hello Powerlink-Team-Kalycito, finally it is working. You just have to configure the jumper reagarding Ethernet Ref Clock to JP9 1-2 Thank you for your help. Best regards, Hassen
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Hello, Thank you for the reply. The driver is inserted correctly and the interface is available. I just noticed that I am using the Avnet expander board(AES-FMC-ISMNET2-G) new version and going through the datasheet to see if I have to make changes to adapt this board to the application. Any information concerning this new board will be helpful. Best regards, Hassen
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Hello! Thank you for the reply. I used the correct boot.bin and the device tree file. Using the ifconfig after inserting the driver using insmod it shows no change in the interface! The same applies also for the example of "Linux on Zynq ARM" and it works fine between the master running on the linux in ARM and the cn node running in the linux PC. When I use the bre build boot.bin and dvicetre.dtb files in the example Zynq hybrid design, I get the same type of error (0x0008) in the oplk_initialize...
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Hello! Thank you for the reply. I used the correct boot.bin and the device tree file. Using the ifconfig after inserting the driver using insmod it shows no change in the interface! The same applies also for the example of "Linux on Zynq ARM" and it works fine between the master running on the linux in ARM and the cn node running in the linux PC. When I use the bre build boot.bin and dvicetre.dtb files in the example Zynq hybrid design, I get the same type of error (0x0008) in the oplk_initialize...
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Hello! going through the steps of the implementation of MN on Zynq Hybrid design using opl v2.6.1 http://openpowerlink.sourceforge.net/doc/2.6/2.6.1/page_zynq_hybrid.html I got these errors: 2016/06/09-17:01:19 INFO GENERIC demo_mn_console: Stack version:V2.6.1 Stack configuration:0x0000000B 2016/06/09-17:01:19 INFO GENERIC Using CDC file: mnobd.cdc Initializing openPOWERLINK stack... 2016/06/09-17:01:19 INFO CONTROL Initializing openPOWERLINK stack Kernel features: 0x0000000b Usable features: 0x0000000b...
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Hello! going through the steps of the implementation of MN on Zynq Hybrid design using opl v2.6.1 http://openpowerlink.sourceforge.net/doc/2.6/2.6.1/page_zynq_hybrid.html I got these errors: 2016/06/09-17:01:19 INFO GENERIC demo_mn_console: Stack version:V2.6.1 Stack configuration:0x0000000B 2016/06/09-17:01:19 INFO GENERIC Using CDC file: mnobd.cdc Initializing openPOWERLINK stack... 2016/06/09-17:01:19 INFO CONTROL Initializing openPOWERLINK stack Kernel features: 0x0000000b Usable features: 0x0000000b...
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Hello! going through the steps of the implementation of MN on Zynq Hybrid design using opl v2.6.1 http://openpowerlink.sourceforge.net/doc/2.6/2.6.1/page_zynq_hybrid.html I got these errors: 2016/06/09-17:01:19 INFO GENERIC demo_mn_console: Stack version:V2.6.1 Stack configuration:0x0000000B 2016/06/09-17:01:19 INFO GENERIC Using CDC file: mnobd.cdc Initializing openPOWERLINK stack... 2016/06/09-17:01:19 INFO CONTROL Initializing openPOWERLINK stack Kernel features: 0x0000000b Usable features: 0x0000000b...
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Hello! going through the steps of the implementation of MN on Zynq Hybrid design using opl v2.6.1 http://openpowerlink.sourceforge.net/doc/2.6/2.6.1/page_zynq_hybrid.html I got these errors: 2016/06/09-17:01:19 INFO GENERIC demo_mn_console: Stack version:V2.6.1 Stack configuration:0x0000000B 2016/06/09-17:01:19 INFO GENERIC Using CDC file: mnobd.cdc Initializing openPOWERLINK stack... 2016/06/09-17:01:19 INFO CONTROL Initializing openPOWERLINK stack Kernel features: 0x0000000b Usable features: 0x0000000b...
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