Activity for George
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George posted a comment on discussion Help
I found an issue - there was a wrong configuration of file stream, it assumes that there are newline characters, after correction all works right: fconfigure $file -translation binary
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: ``` 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data... P.S. and the same as above for time vector: 8.408035545962357e-10 7.56745598000374e-10 7.597128615522043e-10 -1.6284671440047134e-18...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out). Don't quite understand why it works until particular line, there are simple for loops that must works the same for the whole data...
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out)
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Also I tried this file, and script works until it breaks 2.959221488976008 2.9598796175063433 7.026947218616172e-192 -2.81709947717119e+160 -5.332451798449676e-110 I attached source raw file data.raw and test.csv with resulted data for v(osc_out)
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Here it is
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Hello, data was generated from ngspice, and there is a text near to binary representation, or do you mean something different?
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I see that all data saved as double, but when I read file with hex viewer with Little Endian double pattern and get garbage (on screenshot), when pattern is float, it at least generate some meaningful values...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at some points, and not right at others. If I miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at one points, and not right at others. I if miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <time><trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand...
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Hello! Is there a comprehensive explanation of raw binary format? I thought that I understand it right, but I got some strange random errors when reading it with my script (see screenshot attached). Don't understand how it can read right at one points, and not right at others. I if miss the byte size of block, then all consecutive values also should be wrong... I assume that we have <trace1><trace2>...<tracen> in binary double for all traces. Size of block was calculated right, don't understand what's...
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Hello! I finally found the issue, thank you!
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -L/usr/lib/x86_64-linux-gnu/libtclstub8.6.a -L/usr/lib/x86_64-linux-gnu/libtkstub8.6.a -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native...
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build CFLAGS = -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -L/usr/lib/x86_64-linux-gnu/libtclstub8.3.a -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native...
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Hello! I use this command to generate swig wrapper: swig -tcl -DUSE_TCL_STUBS -DUSE_TK_STUBS filter.i And then Make file like this: all: filter.so CC=gcc BUILD=build filter.so: $(BUILD)/filter.o $(BUILD)/filter_wrap.o mkdir -p $(BUILD) $(CC) -shared $(BUILD)/filter.o $(BUILD)/filter_wrap.o -o $(BUILD)/filter.so $(BUILD)/filter.o: filter.h filter.c mkdir -p $(BUILD) $(CC) -c filter.c -fPIC -Wall -O3 -g -march=native -o $(BUILD)/filter.o $(BUILD)/filter_wrap.o: filter_wrap.c filter.h mkdir -p $(BUILD)...
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I tried to provide static /usr/lib/x86_64-linux-gnu/libtcl8.6.a file during .so compilations, and it works as usual with tclsh, but after wraping it throw a Seg fault
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I find that Tcl_AppendResult is provided by libtcl8.6.so library, and tried to add it to wrap, but still no effect.
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Hello! In my tool I have compiled C shared library .so, and I load it into mail application through load. When I wrap my application and run it, I got this: Undefined symbol: Tcl_AppendResult I suspect that some binaries are not there in FreeWrap, is it possible to add them into it, or what else could be the issue? System is Ubuntu. Thank you in advance.
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Got it, thank you!
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Thank you, it is a very valuable information ! :) The only question is reltol - 1e-4 looks too small, no?
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Thank you, it is a very valuable information ! :)
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For now I prefer to use averaged models of power converters, but it is not always possible...
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Hello! I have a general question - what is the best way to improve convergence of circuits with switching converters. I tried: increased abstol and vntol to 1e-3 (voltages and currents in circuit in range of hundreds of amperes/volts), increase chgtol to 1e-12, add lseries in range of 1e-4 ... 1e-3, make all components less ideal, including power sources, inductors, etc. Also I tried to decrease maximum time steps. But unfortunately, I still experienced random time-step too small. What could be done...
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Got it, thank you. Do you have any tips to improve convergence in switching power circuit? I increased abstol, vntol, add lseries, reduces time step, what else could be done? Thank you in advance.
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Got it, thank you. Do you have any tips to improve convergence in switching power circuit? I increased abstol, vntol, add lseries, reduces time step, what else could be done? Thank you in advance.
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do you mean by discrete control the digital circuit with PWM ?
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okay, thank you for detailed explanation, so what could be the modification of circuit elements to avoid it? add bandwidth limiters to elements? i have similar issues with more complex direct field control circuit, it refuses to converge
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Yeah but how to define the order of non-ideality that leads to convergence? Set and try? Also, what is the issue with the algebraic loop for SPICE simulator? it anyway works on solution of the whole system of equations, it doesn't calculate from input to output sequentially from one block to another...
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Don't know why this post in devel forum, please moev it to help, thank you.
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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Hello! I have circuit that implements volt-herz control of induction control with compensation. Circuit is on the screenshot, I can't put online all modules unfortunately. The results are on the second screenshot, that are right. But, if I remove delay from compensation feedback loop, the circuit stops convergence at the first time step, the error is: doAnalyses: TRAN: Timestep too small; initial timepoint: cause unrecorded. The default run option is UIC, but if I do DC-solution before transient...
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and such mechanism exists in commercial SPICEs, for example, in ADS simulator https://people.ece.ubc.ca/robertor/Links_files/Files/ICCAP-2008-doc/icref/icref0713.html
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and such mechanism exist in commercial SPICEs, for example, in ADS simulator https://people.ece.ubc.ca/robertor/Links_files/Files/ICCAP-2008-doc/icref/icref0713.html
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hello, yeah I understand that, just hoped that is not a big issue because of already existing mechanism of aliasing (presence of gnd alias). I need it for my open source project that brings together different physical domains: electrical, magnetic, mechanical, thermal, etc. I want to clearly distinguish for user different domains, do erc check, and each domain has its own reference. For ngspice there is no difference, but for user and highlighting mechanism of domain specific nets it's important....
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Add ability to add custom aliases for global 0 node
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica. Ngspice circuit fires the pulse with value of it's width at start point, openmodelica gives value of width where saw-tooth signal cross the threshold, the true value. This difference affects the result because it accumulates.
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You can see the issue on this screenshot, comparison of ngspice versus openmodelica.
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But the same circuit works correctly in OpenModelica...
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But the same circuit works correct in OpenModelica...
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But the same circuit is work correct in OpenModelica...
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. This is open-loop DC-AC inverter with synchronization. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. This is open-loop DC-AC convertor with synchronization. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Hello, I did it below, thank you
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. PLL block is expanded on second screenshot, and H-bridge is on the third screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components. PLL block is expanded on second screenshot.
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Th circuit is on the screenshot, I can't easily share the netlist because it depends on custom verilog-a components.
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First screenshot is from saw-tooth PWM with 1us max time step, the second with max time step 100us. As you can see, the difference is actually matter.
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This is an example of error that accumulates, white - correct PWM, blue - result from sub-circuit in first post. I consider this as a large error.
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First screenshot is from saw-tooth PWM with 1us max time step, the second with max time step 100us
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This is an example of error that accumulates, white - correct PWM, blue - result from sub-circuit in first post. I consider this as a large error.
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The built-in PWM in hybrid domain also depends on the time-step size....
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So I found an issue - it have problem with generating pulses with duty cycle close to 1. But anyways, I took this model of PWM from this forum, and it does not generate right PWM signal according to control signal. If we use conventional PWM with saw tooth, it switches right at the moment of the control signal equal to ramp signal value, but in this case we have the width of the pulse that was at the trigger moment, and if the switching frequency not high enough, we get mismatch in the signal between...
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Does anyone know what could be the issue here?
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The context is following: I want to use different names for reference in different physical domains, but at the end it must be connected to global 0 node. I was able to do it with global shorting these references to 0 by zero voltage sources, and it works, but it affects the convergence of some circuits.
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The context is following: I want to use different names for reference in different physical domains, but at the end it must be connected to global 0 node. I was able to do it with global shorting these references to 0 by zero voltage sources, and it works, but it affects the convergence of some circuits.
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Hello! Is it possible to define aliases names for 0 node? I tried to use .global for alternative names and short these nodes to 0 by zero value voltage sources, but the issue is that it affects the convergence of some circuits... Thank you in advance.
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Hello! As far as I know, there is no way to define different abstol values for individual voltage nodes and current branches, right? In what application it would be helpful: 1) for example, when we have circuit with low voltage and high voltage parts, in first case we need to compute very small currents, but for high-voltage part it imposes too strict convergence criteria that could lead to fail of simulation. 2) when we have circuit with different natures, for example, the mechanics one and electrical...
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Hello! As far as I know, there is no way to define different abstol values for individual voltage nodes and current branches, right? In what application it would be helpful: 1) for example, when we have circuit with low voltage and high voltage parts, in first case we need to compute very small currents, but for high-voltage part it imposes too strict convergence criteria that could lead to fail of simulation. 2) when we have circuit with different natures, for example, the mechanics one and electrical...
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Super dumb question - how to configure adc in differential mode? Variants: [ (vc_i ramp) ] [ vd(vc_i ramp) ] [ d(vc_i ramp) ] (vc_i ramp) don't work... Upd: found it, sorry [ %vd(vc_i ramp) ]
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Super dumb question - how to configure adc in differential mode? Variants: [ (vc_i ramp) ] [ vd(vc_i ramp) ] [ d(vc_i ramp) ] (vc_i ramp) don't work...
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yes, this is what I wanted, brilliant idea to use the adc/dac bridges, thank you very much!
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I meant that I have to recompile ngspice together with xspice model, there is no way to independently compile only xspice model. This is opposite to the approach that used with verilog-a osdi modules, you can compile them out of source.
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I meant that I have to recompile ngspice to include xspice model to known devices for ngspice. This is opposite to the approach that used with verilog-a osdi modules, you can add it at runtime.
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Hello, yes I know, but the issue is that i need element that can be distributed separately from ngspice, but currently custom XSPICE model could be used only after recompiling together with ngspice :( As far as I know, we cannot use xspice models as shared library
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Hello, yes I know, but the issue is that i need element that can be distributed separately from ngspice, but currently custom XSPICE model could be used only after recompiling together with ngspice :( As far as I know, we cannot use xspice models as shared libraries
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Hello, yes I know, but the issue is that i need element that can be distributed separately from ngspice, but now custom XSPICE model could be used only after recompiling together with ngspice :(
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Hello! Is it possible to make an ideal comparator, that can generate events for time step controlling algorithm? B-sources obviously won't work without step-size limit, what are the another options? I thought about voltage-controlled switches, but not sure if they actually generate events... Thank you in advance
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Hello, with gndref version I don't experience any issues, the circuit is attached to the post. The verilog-a code is: `include "disciplines.vams" `include "constants.vams" module jiles_atherton_hyst_core(p,n,gndref); (*units="", desc="Effective magnetic LENgth of core"*) parameter real L=0.1 from (0:1000); (*units="", desc="Magnetic cross-sectional area of core"*) parameter real AREA=1 from (0:inf); (*units="", desc="Saturation magnetization"*) parameter real MS=1.6e6 from (0:inf); (*units="", desc=""*)...
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Hello, with gndref version I don't experience any issues, the circuit is attached to the post. The verilog-a code is: // Jiles-Atherton hysteresis core Verilog-A model // This file is a part of MDPSBLib (Multi-domain physics SPICE-based library) // Enhanced as described in "Simulation and MOdeling of Nonlinear Magnetics" // by Williams, Vogelsong, and Kundert, as found on www.designers-guide.org. // MIT License // // Copyright (C) 2024 George Yashin georgtree@gmail.com // // Permission is hereby...
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Hello, with gndref version I don't experience any issues, the circuit is attached to the post. The verilog-a code is: // Jiles-Atherton hysteresis core Verilog-A model // This file is a part of MDPSBLib (Multi-domain physics SPICE-based library) // Enhanced as described in "Simulation and MOdeling of Nonlinear Magnetics" // by Williams, Vogelsong, and Kundert, as found on www.designers-guide.org. // MIT License // // Copyright (C) 2024 George Yashin georgtree@gmail.com // // Permission is hereby...
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I just finished all conversions of my Verilog-a components - all components that assume implicit ground for internal nodes (that used as a computational nodes for variables store), and it is not a thermal node, create issues with dc-convergence. After adding explicit node gndref and connect it externally to 0 (global ground), all components work as it was on old system. For example: This doesn't work: `include "disciplines.vams" `include "constants.vams" module park_transform(alpha, beta, theta,...
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Original version of this element worked with implicit ground, but on new system with more modern compilator it works only with explicit ground connection. Or maybe I didn't understand your question? The rest of the models with the same issue (implicit ground) works as it worked previously with similar modification. I think it is not the issue of open-vaf because it has pre-compiled binary...? Maybe issue in ngspice interface to open-vaf ABI?
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it would be also interesting to check what clang compiler could produce....
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Original version of this element worked with implicit ground, but on new system with more modern compilator it works only with explicit ground connection. Or maybe I didn't understand your question? The rest of the models with the same issue (implicit ground) works as it works previously. I think it is not the issue of open-vaf because it has pre-compiled binary...? Maybe issue in ngspice interface to open-vaf ABI?
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Old version of this element worked with implicit ground, but on new sustem with more modern compilator it works only with explicit ground connection. Or maybe I didn't understand your question? The rest of the models with the same issue (implicit ground) works as it works previously. I think it is not the issue of open-vaf because it has pre-compiled binary...? Maybe issue in ngspice interface to open-vaf ABI?
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Old version of this element worked with implicit ground, but on new sustem with more modern compilator it works only with explicit ground connection. Or maybe I didn't understand your question? The rest of the models with the same issue (implicit ground) works as it works previously.
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground. if I add ground terminal explicitly to element and reference it in model for internal computational nodes, all works fine. i understand that it is super-strange, but only explicit ground reference allow circuit to converge. This version of the model works: `include "disciplines.vams" `include "constants.vams" module jiles_atherton_hyst_core(p,n,gndref); (*units="", desc="Effective magnetic LENgth of core"*)...
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground. if I add ground terminal explicitly to element and reference it in model for internal computational nodes, all works fine. i understand that it is super-strange, but only explicit ground reference allow circuit to converge.
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground. if I add ground terminal explicitly to element and reference it in model for internal computational nodes, all works fine.
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground.
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground implicitly, if it is referenced to ground node explicitly, all works as intended.
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UPDATE Finally, I found the source of error - the reference of internal nodes to global ground, if it is referenced to one of the other node, all works as intended.
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I found the issue that united many non-converging components - the presence in Verilog-A code with integral contribution: V(node) <+ idt(variable); especially if it is referenced to 0 (ground)
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I found the issue that united many non-converging components - the presence in Verilog-A code with integral contribution: V(node) <+ idt(variable);
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Hello, thank you for suggestion. But how it can be possible? Some difference in how compiler optimize floating point numbers/operations?
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