3D - plate for hotglue added
The KRYON of Magnetic Service - fixed
3D - tool for crafting coils added (3)
3D - tool for crafting coils added (2)
2.1.6 - RM72x32x15 added
3D - tool for crafting coils added
3D - mods due to filament change to PLA+
3D - fixed sizes for other magnet type
3D - new experiment plate added
3D - update to FreeCAD 1.0
fpga - system/analyze - LO 125 MHz ready, IF clock to be checked (1a)
fpga - system/analyze - LO 125 MHz ready, IF clock to be checked
fpga - system/analyze - new LO and IF clock pulses for target receive frequency
HW - initial directory setup
tof_www_apps - I/Q Analyzer - 2_Analyze-Ramp__Claude-Sonnet-4.py multiple strange errors remain
tof_www_apps - I/Q Analyzer - 1_Analyze-Ramp__ChatGPT-4o.py works
fpga - system - wrong CORDIC connection fixed
fpga - system - AXI SmartInterconnect for LITE and DMA used again (1a)
tof_www_apps - GPS data dropouts fixed - changed to 38400 Baud
tof_www_apps - startup problem with gdb fixed - Makefiles -O3 added
fpga - system - AXI SmartInterconnect for LITE and DMA used again
fpga - system - DMA added again (1a)
fpga - system - DMA added again
fpga - revert to 20250521b_42fc6244 but use latest analyze - booting GOOD
fpga - system - replace new AXI smartconnect by old but working AXI Interconnect - DMA also
fpga - system - replace new AXI smartconnect by old but working AXI Interconnect (1a)
fpga - system - replace new AXI smartconnect by old but working AXI Interconnect
fpga - analyze - CORDIC modified (2)
fpga - analyze - CORDIC modified
fpga - analyze - DDS to 10MHz and no DAC anymore (4a)
fpga - analyze - DDS to 10MHz and no DAC anymore (4)
fpga - analyze - DDS to 10MHz and no DAC anymore (3)
fpga - analyze - DDS to 10MHz and no DAC anymore (2)
fpga - analyze - DDS to 10MHz and no DAC anymore
fpga - analyze - DAC2 output removed
Merge branch 'main' of ssh://git.code.sf.net/p/redpitaya-tof/code into main
fpga - analyze - 62.5 MHz sync reduced to 100 us
fpga - analyze - 62.5 MHz sync reduced to 100 us (2)
fpga - analyze - 62.5 MHz sync reduced to 1 ms
fpga - analyze - FIFO FSM decimation by 2
tof_www_apps - FIFO buffer 2.000Mps - auto-adjusting sync point (2)
tof_www_apps - FIFO buffer - auto-adjusting sync point
fpga - system - AXI interfacing enhanced
tof_www_apps - com_ubx.c - GPS buffering fixed
of_www_apps - ToF_IQdata - DMA - reducing buffers
fpga - FSM Ramp - once a second only
Merge branch 'main' of ssh://git.code.sf.net/p/redpitaya-tof/code
tof_www_apps - segfault somewhere around ub_receive() ?
fpga - FSM Ramp - step values delay extended
fpga - FSM Ramp - step values okay (1c)
fpga - FSM Ramp - step values okay (1b)
fpga - FSM Ramp - step values okay (1a)
fpga - FSM Ramp - fixed (1a)
fpga - FSM Ramp - fixed
fpga - AXI SmartConnect DMA - upgrade (5a)
fpga - AXI SmartConnect DMA - upgrade (5)
fpga - AXI SmartConnect DMA - upgrade (4a)
fpga - AXI SmartConnect DMA - upgrade (4)
fpga - AXI SmartConnect DMA - upgrade (3)
Merge branch 'main' of ssh://git.code.sf.net/p/redpitaya-tof/code into main
fpga - AXI SmartConnect DMA - upgrade (2)
fpga - AXI SmartConnect DMA - upgrade
fpga - FSM ramp enhanced (2)
fpga - AXI DMA added - settings added (2)
fpga - FSM ramp enhanced
tof_www_apps - ToF_IQdata - DMA - timing info added
fpga - AXI DMA added - settings added
fpga - AXI DMA added (2)
tof_www_apps - ToF_IQdata - DMA - round trip works
tof_www_apps - ToF_IQdata - DMA - single shot works
tof_www_apps - ToF_IQdata - DMA engine needs physical DDR, not virtual address
fpga - AXI DMA added - chain buffers and I/Q buffers set
fpga - AXI DMA added - more modifications done
fpga - AXI DMA added - first modifications done
fpga - AXI DMA added (2)
fpga - AXI DMA added
tof_www_apps - ToF_App - step limits try
fpga - analyze - fsm_ramp_fifo fixed
tof_www_apps - ToF_App - initial FIFO packets received
fpga - analyze - fsm_ramp_fifo and GPIOx assignments modified (2)
fpga - analyze - fsm_ramp_fifo and GPIOx assignments modified
fpga - DAC waveforms added (3)
tof_www_apps - ToF_App - additional instruments added
fpga - analyze - CORDIC output width from 10 to 11 bits changed (2)
fpga - analyze - CORDIC output width from 10 to 11 bits changed
tof_www_apps - ToF_App - modifications for phase analyzer
fpga - analyze - time32 FSM added (2)
fpga - analyze - time32 FSM added
fpga - analyze ramp - new FSM added (2)
fpga - analyze ramp - new FSM added
fpga - docs added
fpga - DAC waveforms added (2)
fpga - DAC waveforms added
fpga - adjusted amplitude of 15.625 MHz output to 750 mVpp
fpga - FSM_FIFO-CORDIC - Simulations added
fpga - FSM fifo/cordic - TUSER for timing of next planned FSM added
tof_www_apps - ToF_App - AXI4Stream-FIFO works (2)
fpga - FSM fifo/cordic and DDS1024 - fixed
fpga - removing RedPitaya no more needed stuff (2)
fpga - removing RedPitaya no more needed stuff