Cary R.

Hi Srini, We normally only use SourceForge for the mailing list and for release distribution. I think Steve requested you to use to discuss this on the mailing list. Please post this to the iverilog-devel mailing list. The short answer is look at ivtest which is our regression environment and determine how to integrate your tests into that environment. For your development I completely understand your desire to have your tests Makefile driven and it should be possible to architect your tests so they...

You need to clock on the edit link. I updated it to VHDL since I assume that is what you were trying to do.

VHDL: rotate support for simulation

Is this for VHDL? If so please add VHDL to the beginning of the title.

iverilog creates infinite loop

I can confirm that both V10 and devel are advancing in time, but the simulations did not produce any output or finish. V0.9 did produce output and completed.

vvp incorrectly exits on termination of a begin/end

I can confirm V10 produces different results then devel which produced the following: Incr/decr operators... line 91, CHECK_RES line 91-1, CHECK_RES line 91-2B, CHECK_RES line 91-B, cleared $ID111 line 91-C, done line 91: completed line 92, CHECK_RES line 93, CHECK_RES line 94, CHECK_RES line 100, arithmetic line 103, CHECK_RES in $L59... incr passcount... done test complete: 30 passes, 0 fails Which is more than you indicated above.