User Activity

  • Posted a comment on discussion ngspice-users on ngspice

    Is there any document with reserved words? Wow, how much time I wasted doing tests and it never occurred to me that resistor would be a reserved word.

  • Posted a comment on discussion ngspice-users on ngspice

    GOOD, thanks.

  • Posted a comment on discussion ngspice-users on ngspice

    $ src/ngspice test.cir Warning: can't find the initialization file spinit. ****** ** ngspice-43 : Circuit level simulation program ** Compiled with KLU Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2024, The ngspice team. ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html ** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html ** Creation Date: Tue Sep 24 06:03:26...

  • Posted a comment on discussion Help on ngspice

    I'm learning how to use Verilog-A with NGspice and I'm having a similar problem, I've tried all the alternatives and I keep getting the error message below, my code at the moment is as follows: verilog-A file: resistor.va `include "disciplines.vams" module resistor(p, n); inout p, n; electrical p, n; parameter real r = 1k; // Resistência de 1k ohm analog begin V(p, n) <+ I(p, n) * r; // Lei de Ohm: V = I * R end endmodule Circuit file: test.cir * Teste de resistor Verilog-A *.hdl resistor.va ; Inclui...

  • Modified a comment on discussion ngspice-users on ngspice

    I am studying how to simulate circuits using Verilog-A and NGspice, I tried the circuits below, but it does not recognize the component in the .model directive, what is wrong? Teste de resistor Verilog-A .model resistor resistor V1 p 0 dc 1 ; Fonte de 1V N1 p 0 resistor ; Instancia o resistor .control pre_osdi ./resistor.osdi tran 1n 10n ; Simulação no domínio do tempo por 10ns print V(p) ; Mostra a tensão no nó p .endc .end Verilog-A: `include "disciplines.vams" module resistor(p, n); inout p, n;...

  • Modified a comment on discussion ngspice-users on ngspice

    I am studying how to simulate circuits using Verilog-A and NGspice, I tried the circuits below, but it does not recognize the component in the .model directive, what is wrong? Teste de resistor Verilog-A .model resistor resistor r=2 V1 p 0 dc 1 ; Fonte de 1V N1 p 0 resistor ; Instancia o resistor .control pre_osdi ./resistor.osdi tran 1n 10n ; Simulação no domínio do tempo por 10ns print V(p) ; Mostra a tensão no nó p .endc .end Verilog-A: `include "disciplines.vams" module resistor(p, n); inout...

  • Posted a comment on discussion ngspice-users on ngspice

    I am studying how to simulate circuits using Verilog-A and NGspice, I tried the circuits below, but it does not recognize the component in the .model directive, what is wrong? * Teste de resistor Verilog-A *.hdl resistor.va ; Inclui o arquivo Verilog-A .model resistor resistor r=2 V1 p 0 dc 1 ; Fonte de 1V N1 p 0 resistor ; Instancia o resistor .control pre_osdi ./resistor.osdi tran 1n 10n ; Simulação no domínio do tempo por 10ns print V(p) ; Mostra a tensão no nó p .endc .end Verilog-A: `include...

  • Posted a comment on ticket #79 on DEPRECATED > GNU ARM Eclipse

    So I'm studying the ASF (XDF-ASF) from atmel to better identify the pattern used...

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