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  • Posted a comment on discussion Technology on openPOWERLINK

    Hi, I know that in Powerlink we can do all the things that you mentioned, but our use case is a different one. We need to completely reassign ID's to a full plant, to change its behavior. Let's say that when the plant is supposed to work clockwise ID's are assigned from 1 to 64, in ascending order. But sometimes the same plant needs to work counterclockwise and this requires to reassign all ID's in descending order, from 64 to 1. So it's not just a matter of replacing or adding a couple of nodes....

  • Posted a comment on discussion Porting on openPOWERLINK

    Hi there, we are using openPOWERLINK on Altera Cyclone IV FPGA with a NIOS softcore running the sw stack. We are also using freeRTOS as OS. On the same softcore we are running a few applicative tasks, that is our application is running on the stack processor instead of using a separate host processor. This is due to the fact that our application is quite simple and requires a lmited amount of CPU/memory. Nevertheless, one of the application task should run periodically, every millisecond. What we...

  • Posted a comment on discussion Technology on openPOWERLINK

    Hello Wolfgang, we are also interested in DNA. The application in our case requires to use several nodes on the bus (up to 80). The customer whants to have the freedom to modify the plant adding/removing devices maybe in the middle of the nodes chain, depending on particular needs. Manually re-assigning ID's is not an option (devices will be hard to reach once thay have been installed). We are using Altera Cyclon IV FPGA. I guess DNA implementation may require modifications in IP cores too. We are...

  • Posted a comment on discussion Technology on openPOWERLINK

    Hello everybody, I have found the following issue with cnLossSoc, cnLossPreq, cnCrcErr (objects 0x1C0B, 0x1C0D, 0x1C0F) threshold (sub-index 3) setting: 1) when kNmtGsResetCommunication event is processed, communication part of OD is reset to default values (value 15, only one SoC/Preq frame loss is tolerated) . Also internal data structure used by the stack is updated accordingly. That is: - 0x1C0B:03 is set to 15 - 0x1C0D:03 is set to 15 - 0x1C0F:03 is set to 15 - cnLossSoc.threshold is set to...

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carlonenna
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2020-07-01 08:43:33

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