Beck Hsieh

Hi Jason, As shown in the Attached Files. Thank you! Beck 2017-10-11 14:38 GMT-05:00 Jason Fuller jcfuller@users.sf.net: Beck, I cannot download from dropbox. Please attach file here. Volt-var optimization https://sourceforge.net/p/gridlab-d/discussion/842562/thread/fcddaf1e/?limit=25#61ec Sent from sourceforge.net because you indicated interest in https://sourceforge.net/p/gridlab-d/discussion/842562/ To unsubscribe from further messages, please visit https://sourceforge.net/auth/subscriptions/...

Jason, Thank you for your rapidly reply. To simplify my question, i have provided the specific glm and results. In the simulation, we assume: (1) the voltage regulator can response fast (1 s delay time) after violated voltage be detected. (2) Cap#1 delay time is 600s, and Cap#2 delay time is 1s. Simulation result indicates that the setting of Cap#1 delay time seems will interfere with the switch time of voltage regulator (eahc n*600s, n = 1,2,3...), the glm file and simulation results in EXCEL form...

Dear sir, I'm try to find out the programming logical about the embedded Volt-var optimization in gridlab-D. I used the sample glm file entitled CRV_13_Node/IEEE_13_house_vvc.glm. From the analyses results,i can't find out a routine logical. I have try many scenarios with different delay time setting for Reg#1, and finally i found two conditions i can't explain: (1) Even the voltage_measurement points (2201+-20V) have over the band-center setting values and the delay time have far reached, but the...