Aodhan Murray

Bug Fix XSpice Verilog Vector Input Issue #686

XSpice Verilog Vector Input Bug

Confirmed bug reviewing ngspice-43 source within src/xspice/verilog/verilator_shim.cpp:43 I found the following macro which is used to set the inputs: #define VL_DATA(size, name, msb, lsb) \ if (index >= msb - lsb + 1) { \ index -= msb - lsb + 1; \ } else if (msb == 0 && lsb == 0) { \ topp->name = val ? 1 : 0; \ return; \ } else { \ if (val) \ topp->name |= (1 << (msb - index)); \ else \ topp->name &= (1 << (msb - index)); \ return; \ } Line 53 of the file is missing a ~. When a zero is set it would...

Thanks for taking a look. Here's my output with input reg [8:0] data with no other changes. Initial Transient Solution -------------------------- Node Voltage ---- ------- vcc 3.3 d7 3.3 d6 0 d5 3.3 d4 3.3 d3 3.3 d2 3.3 d1 3.3 d0 3.3 en 3.3 ven#branch 0 vd0#branch 0 vd1#branch 0 vd2#branch 0 vd3#branch 0 vd4#branch 0 vd5#branch 0 vd6#branch 0 vd7#branch 0 vcc#branch 0 TEST: data=001111110

Hi, Apologies if this has already been posted about, I've struggled to find any relevant posts or documentation about this issue. I'm fairly new to both ngspice and verilog so it may be a user error. I have a very simple ngspice circuit and verilog module showcasing my issue. I have a register input [7:0] "data" which is mapped to ngspice nodes from power supplies set to vcc or 0. My issue is the circuit only registers 1's that are continuous from the LSB e.g. 10111111 is mapped as 00111111. I've...

Hi, Apologies if this has already been posted about, I've struggled to find any relevant posts or documentation about this issue. I'm fairly new to both ngspice and verilog so it may be a user error. I have a very simple ngspice circuit and verilog module showcasing my issue. I have a register input [7:0] "data" which is mapped to ngspice nodes from power supplies set to vcc or 0. My issue is the circuit only registers 1's that are continuous from the LSB e.g. 10111111 is mapped as 00111111. I've...