User Activity

  • Posted a comment on discussion Getting Started on openPOWERLINK

    Hi, What is the Powerlink cycle time you are using for this test setup ? In the mean time, could you also build the CN in release build and retry ? Best Regards, #aeicoriiotteam

  • Posted a comment on discussion Open Discussion on openPOWERLINK

    Hi Omar, which board are you using ? Can you provide the steps used by you. Do you have problem when you load the powerlink module ? Best Regards, #aeicoriiotteam

  • Posted a comment on discussion Open Discussion on openPOWERLINK

    Hi Bhusan, for openPowerlink you can find documentation and guides here. If there are any queries related to the MN and CN demos, you can mention it here. For the opc ua gateway, you probably can try posting a ticket at the menioned github repo. If you need specific opc ua support , please dm. Best Regards, #aeicoriiotteam

  • Posted a comment on discussion Getting Started on openPOWERLINK

    Hi Geo, there are restrictions from a spec point of view in sending strings via PDO. Please refer this thread for more info. But theoretically you can do it with some manual editing. For critical realtime communication, PDO is the only way of exchanging data. To exchange a fixed size string, you can handle it in application process loop where you convert it into multiple byte arrays and transfer it breaking (or overriding) the spec/stack restrictions. You can use SDO for normal string transfers,...

  • Posted a comment on discussion Getting Started on openPOWERLINK

    Hi William, It depends on the network configuration i.e. MN calculates the time required for the number of Poll requests and responses configured and then decides a time for txing the SoA frame, where SoC is the start time reference. Note that there is a slight difference in behavior between different devices in how they optimize the poll response timeout. Best Regards, #aeicoriiotteam

  • Posted a comment on discussion Getting Started on openPOWERLINK

    Hi Steph, Tomas, Sorry for the delay in getting back. The Zynq hybrid design is based on the Zc702 which has a 1GB shared DDR3 between ARM Linux (PS) and Microblaze (PL). For the hybrid master design, this entire memory is divided into 3 sections, as it uses the dual-processor-shared-memory interface library for communication between the OPLK application (on Linux) and communication stack (PCP or Microblaze). The 3 sections are : - Memory visible to Linux (kernel), - Common memory - PCP application...

  • Posted a comment on discussion Getting Started on openPOWERLINK

    Great. Cheers !!

  • Posted a comment on discussion Porting on openPOWERLINK

    Hi Johannes, thanks for the update. Good to know. Let me know if you need any support.

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