SystemC Integrations

Coco® is a multi-language code coverage tool. Automatic source code instrumentation is used to measure test coverage of statements, branches and conditions. Executing a test suite against an instrumented application produces data that can later be analyzed. This analysis can be used to understand how much of the source code has been hit by tests, which additional tests need to be written, how the test coverage changed over time and more. Identify redundant tests, untested or dead code. Identify the impact of a patch on the code and code coverage & your testing. Coco supports statement coverage, branch coverage, MC/DC and other levels. Linux, Windows, RTOS and others. Using GCC, Visual Studio, embedded compilers and more. Choice of different report formats (text, HTML, XML, JUnit, Cobertura). Coco can also be integrated with various build, test and CI frameworks like JUnit, Jenkins and SonarQube.

Linux, Windows, RTOS and others. Using gcc, Visual Studio, embedded compilers and more. Merging multiple execution reports to provide advanced analysis and more outstanding features. Assess and optimize code performance with Coco’s built-in Function Profiler.

ModelSim simulates behavioral, RTL, and gate-level code, delivering increased design quality and debug productivity with platform-independent compilation. Single kernel simulator technology enables transparent mixing of VHDL and Verilog in one design. ModelSim packs an unprecedented level of verification capabilities into a cost-effective HDL simulator and is ideally suited for the verification of small and medium-sized FPGA designs, especially designs with complex, mission-critical functionality. ModelSim’s advanced code coverage capabilities provide valuable metrics for systematic verification. Plus, ModelSim’s ease of use lowers the barriers to leveraging verification resources. All coverage information is stored in the highly efficient UCDB database. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs. An easy-to-use and unified environment provides FPGA designers with the advanced capabilities they need for debugging.