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About

Ansys PathFinder-SC is a high-capacity solution to help you plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against electrostatic discharge (ESD). Ansys PathFinder-SC identifies and isolates the root causes of design issues that can cause chip failure from charged-device model (CDM), human body model (HBM), or other ESD events. It’s high-capacity, cloud-native architecture can enlist thousands of compute cores for fast full-chip turnaround. PathFinder-SC is certified by major foundries for current density checks and ESD sign-off. PathFinder-SC’s integrated data modeling, extraction and transient simulation engine is an end-to end solution for ESD verification. The single-pass use model reads industry-standard design formats, sets up ESD rules, extracts the RCs for the power network, and performs ESD simulations to analyze root causes and provide fix and optimization feedback, all within a single tool.

About

Your design’s testability can determine how fast your product gets to manufacturing. But testing at the physical stage is too late to catch commonly made mistakes that lead to expensive delays. XJTAG® DFT Assistant integrates directly within your Altium Designer unified design environment, running Design For Test (DFT) checks on boundary scan chains directly on the schematic diagram. Easily confirm that scan chains are correctly connected to each JTAG-enabled device in your design, and confirm that each signal in the chain has been accurately connected and terminated. XJTAG® DFT Assistant performs the checks needed to ensure your JTAG chain is right before you finalize your layout. XJTAG® Chain Checker weeds out the commonly made errors, reports issues early in the process and lets you get past the mistakes that could hinder JTAG testing.

Platforms Supported

Windows
Mac
Linux
Cloud
On-Premises
iPhone
iPad
Android
Chromebook

Platforms Supported

Windows
Mac
Linux
Cloud
On-Premises
iPhone
iPad
Android
Chromebook

Audience

Enterprises interested in an electrostatic discharge simulation software to plan, verify and sign-off IP and full-chip SoC designs

Audience

PCB design platform for companies wanting to identify testability issues directly on your schematic

Support

Phone Support
24/7 Live Support
Online

Support

Phone Support
24/7 Live Support
Online

API

Offers API

API

Offers API

Screenshots and Videos

Screenshots and Videos

Pricing

No information available.
Free Version
Free Trial

Pricing

No information available.
Free Version
Free Trial

Reviews/Ratings

Overall 0.0 / 5
ease 0.0 / 5
features 0.0 / 5
design 0.0 / 5
support 0.0 / 5

This software hasn't been reviewed yet. Be the first to provide a review:

Review this Software

Reviews/Ratings

Overall 0.0 / 5
ease 0.0 / 5
features 0.0 / 5
design 0.0 / 5
support 0.0 / 5

This software hasn't been reviewed yet. Be the first to provide a review:

Review this Software

Training

Documentation
Webinars
Live Online
In Person

Training

Documentation
Webinars
Live Online
In Person

Company Information

Ansys
Founded: 1970
United States
www.ansys.com/products/semiconductors/ansys-pathfinder-sc

Company Information

Altium
Founded: 1985
United States
www.altium.com/products/extensions/platform-extensions/xjtag/overview

Alternatives

Alternatives

JTAG Maps

JTAG Maps

Altium
Autodesk EAGLE

Autodesk EAGLE

Autodesk

Categories

Categories

Integrations

Allegro X Design Platform
OrCAD X

Integrations

Allegro X Design Platform
OrCAD X
Claim Ansys PathFinder and update features and information
Claim Ansys PathFinder and update features and information
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Claim XJTAG DFT Assistant and update features and information