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verilog compiler

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Description

A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

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Categories

Simulations, Education

License

BSD License

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Additional Project Details

Languages

English

Intended Audience

Information Technology, Advanced End Users, Developers, End Users/Desktop, Quality Engineers, Other Audience

User Interface

Command-line

Programming Language

VHDL/Verilog, Java

Registered

2009-08-21

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