Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.

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License

BSD License

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Additional Project Details

Operating Systems

Linux

Intended Audience

Science/Research, Telecommunications Industry

Programming Language

VHDL/Verilog

Related Categories

VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2008-04-27