The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology.

UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list.

Moreover, the graphical interface lets the user observe the structure of the generated testbench. Files can be accessed easily by double clicking on the graphical view. Simulation can be launched directly from the tool.

Project Samples

Project Activity

See All Activity >

License

Apache License V2.0, GNU General Public License version 3.0 (GPLv3)

Follow UVE

UVE Web Site

Other Useful Business Software
Our Free Plans just got better! | Auth0 Icon
Our Free Plans just got better! | Auth0

With up to 25k MAUs and unlimited Okta connections, our Free Plan lets you focus on what you do best—building great apps.

You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
Try free now
Rate This Project
Login To Rate This Project

User Reviews

Be the first to post a review of UVE!

Additional Project Details

Operating Systems

Linux, BSD, Windows

User Interface

Qt

Programming Language

C++

Related Categories

C++ Electronic Design Automation (EDA) Software

Registered

2014-10-30