This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

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Additional Project Details

Languages

English

Intended Audience

Developers, Education, Science/Research

Programming Language

Assembly

Registered

2003-06-02