parseverilog (SystemVerilog) -- EDAUtils parseverilog 20260908

IEEE LRM-compliant SystemVerilog parser with Java, Python, Tcl APIs

Keywords: SystemVerilog parser, Verilog parser, IEEE 1800, Java API, Python API, Tcl API, RTL parser

Release: 20260908
File: parseverilog-20260908.tar.gz (Linux x86_64; needs a Java 17 or newer JRE on PATH)
License: free to use with the bundled evaluation licence; commercial licences from help@edautils.com

Install and run

tar xzf parseverilog-20260908.tar.gz
cd parseverilog/*/ && source setup_env.sh      # or setup_env.csh / setup_env.bat
parseverilog -help

Links

• Canonical download page: https://edautils.ai/download?tool=ParseverilogSystemverilog
• Documentation: https://edautils.com/
• All EDAUtils tools: https://edautils.com/
• Support: help@edautils.com

EDAUtils builds free and commercial EDA utilities for RTL and IP integration: SystemVerilog, Verilog and VHDL parsers and converters, IP-XACT (IEEE 1685) tools, UPF (IEEE 1801) and SDC tools, Liberty and VCD parsers, SoC integration and RTL hierarchy manipulation, testbench and register-model generators.

{
  "@context": "https://schema.org",
  "@type": "SoftwareApplication",
  "name": "parseverilog (SystemVerilog)",
  "softwareVersion": "20260908",
  "fileFormat": "application/gzip",
  "operatingSystem": "Linux",
  "applicationCategory": "DeveloperApplication",
  "applicationSubCategory": "Electronic Design Automation",
  "downloadUrl": "https://edautils.ai/download?tool=ParseverilogSystemverilog",
  "installUrl": "https://edautils.ai/download?tool=ParseverilogSystemverilog",
  "url": "https://edautils.com/",
  "author": {
    "@type": "Organization",
    "name": "EDAUtils",
    "url": "https://edautils.com/",
    "email": "help@edautils.com"
  },
  "publisher": {
    "@type": "Organization",
    "name": "EDAUtils",
    "url": "https://edautils.com/"
  },
  "offers": {
    "@type": "Offer",
    "price": "0",
    "priceCurrency": "USD",
    "description": "Free to evaluate with the bundled licence; commercial licences from help@edautils.com"
  },
  "softwareRequirements": "Java 17 or newer JRE on PATH",
  "datePublished": "2026-09-08",
  "description": "IEEE LRM-compliant SystemVerilog parser with Java, Python, Tcl APIs",
  "keywords": [
    "SystemVerilog parser",
    "Verilog parser",
    "IEEE 1800",
    "Java API",
    "Python API",
    "Tcl API",
    "RTL parser"
  ],
  "softwareHelp": "https://edautils.com/"
}