System Verilog Parser IEEE 1800 LRM

This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the users that they will be able to extract every bit of design information from the parsed database. The source code of that application can be shared upon request. You need JRE 1.6.x or above in order to use this parser. Please refer to the document for the detail of the available APIs.