SOC Description Language - Browse Files at SourceForge.net

The interactive file manager requires Javascript. Please enable it or use sftp or scp.
You may still browse the files here.

Name	Modified	Size	InfoDownloads / Week
PDF_docs	2011-04-10		0
Source	2011-04-10		0
Totals: 2 Items			0

Other Useful Business Software

Try Google Cloud Risk-Free With $300 in Credit

No hidden charges. No surprise bills. Cancel anytime.

Use your credit across every product. Compute, storage, AI, analytics. When it runs out, 20+ products stay free. You only pay when you choose to.

Start Free

Gemini 3 and 200+ AI Models on One Platform

Access Google's best plus Claude, Llama, and Gemma. Fine-tune and deploy from one console.

Build generative AI apps with Vertex AI. Switch between models without switching platforms.

Start Free

Try Google Cloud Risk-Free With $300 in Credit

No hidden charges. No surprise bills. Cancel anytime.

Use your credit across every product. Compute, storage, AI, analytics. When it runs out, 20+ products stay free. You only pay when you choose to.

Start Free

Recommended Projects

Alliance CAD System
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
The Register Description Language (RDL)
The Register Description Language (RDL) is an object modeling language used to specify and implement software accessible hardware registers and memories. A RDL compiler can create synthesizable HDL, documentation, driver code, system-c models, and more.
IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Free Verilog VHDL IP-XACT Liberty Utils
1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)
Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.

SOC Description Language Files

Get an email when there's a new version of SOC Description Language