SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane.

Project Activity

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Categories

Simulation

License

GNU General Public License version 3.0 (GPLv3)

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Additional Project Details

Intended Audience

Engineering, Science/Research

User Interface

Command-line

Programming Language

VHDL/Verilog

Related Categories

VHDL/Verilog Simulation Software

Registered

2012-02-24