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SmGen

beta

Verilog Finite State Machine (FSM) Code Generator

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Description

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

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Additional Project Details

Intended Audience

Science/Research, Developers, Engineering

User Interface

Command-line

Programming Language

Perl, VHDL/Verilog

Registered

2010-06-11

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