| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| CmdLine-0.12.5-x86-418d3538ee.zip | 2026-09-29 | 22.2 MB | |
| CmdLine-0.12.5-x64-418d3538ee.zip | 2026-09-29 | 22.5 MB | |
| WindowsDecompiler-0.12.5-x86-418d3538ee.zip | 2026-09-29 | 24.7 MB | |
| WindowsDecompiler-0.12.5-x64-418d3538ee.zip | 2026-09-29 | 24.9 MB | |
| Reko-0.12.5-x86-418d3538ee.msi | 2026-09-29 | 20.4 MB | |
| Reko-0.12.5-x64-418d3538ee.msi | 2026-09-29 | 20.5 MB | |
| README.md | 2026-09-28 | 4.5 kB | |
| Version 0.12.5 source code.tar.gz | 2026-09-28 | 55.4 MB | |
| Version 0.12.5 source code.zip | 2026-09-28 | 59.5 MB | |
| Totals: 9 Items | 250.0 MB | 18 | |
A maintenance release mostly with bugfixes.
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Fix NativeProxy builds (credit to @smx-smx)
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X86TextAssembler assembled SHRD as SHLD
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Added InstructionComparers to all architectures. We need InstructionComparers to make procedure fingerprinting possible.
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Added a framework for binary fingerprint identification. Future work could ingest run-time libraries and recognize well known procedures, in order to build fingerprint libraries.
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Generate global variable names from strings, by mangling them.
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Added support for PS2 Emotion Engine
- Added support for disassembling and lifting PS2 EE binaries.
- Added support for PS2 EE calling convention.
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Refactored MIPS disassembler and rewriter classes into namespaces The PS2 EE GP registers are 128 bits, but the memory accesses are only 32 bits. We need to truncate the GP registers before using them in effective memory addresses.
Credit to @smx-smx for originating the code.
Feature: support for the PS2 Emotion Engine
This commit introduces support for the PS2 Emotion Engine, a.k.a. MIPS 5900. It introduces a new ISA for the MIPS architecture, as well as some new registers.
This is not a complete implementation yet, but implements many of the new instructions. Future commits will fill out the missing decoders and lifters.
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Corrected zSeries disassembled constants so they are rendered as the "z/Architecture Principles of Operation" manual does.
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Added many more zSeries lifters to improve coverage of IBM binaries.
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Added more Blackfin instruction decoders.
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Feature: IntrinsicProcedure.IsInstanceOf. Use this new method to determine whether an intrinsic is an instance of a possibly generic intrinsic.
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Enhancement: pedantic checking of RtlAssignment argument sizes.
We are allowing RtlAssignments with
srcanddstof different sizes. In some cases, we let this slip through, but in other cases it's an actual bug and should be fixed. The#if PENDATICin theRtlAssignmentconstructor is a reminder that this should be mainline, not commented out.About 400 unit tests fail when
PEDANTICis set. -
Feature: add RegisterBank to Reko.Core.Machine
This class is used for lookups from register names or StorageDomains.
Some TLCS900 instructions were being lifted incorrectly, resulting in assigments with unequally sized left- and right-hand sides.
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Feature: first cut of RiscOS AIF loader.
Initial support for RiscOS AIF images. More info can be extracted from AIF binary images, but it's a start.
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Fix: MN103 disassembler and lifter
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The
abs32method in the MN103 disassembler was generatingAddressoperands instead of memory accesses of absolute addresses -
Several instructions that affect the condition codes were not lifted by the
MN103Rewritercorrectly. The results of an ALU operation must always be fed to aCOND()intrinsic before being assigned to the CPU status word register.
Fix: MN103 syscall lifter
The MN103
syscall #Nlifter wasn't supplying the operand as an argument to thesyscallintrinsic function.Classify MN103 CALLS instructions
Use InstrClass.Call for the direct d16 and d32 forms and InstrClass.CallInd for the register-indirect form. Add focused disassembler and rewriter coverage, and add Alexander Rassokhin to AUTHORS.
Fix MN103 decoding of (d32,SP) operands and CALLS with 32-bit displacement
The FC-prefix (6-byte) page of the MN103 disassembler had two decoding bugs:
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The d32_sp mutator was defined with reg_relative_u16, so every (d32,SP) memory operand (the MOV/MOVBU/MOVHU forms at FC 8x/9x/Bx) read only 16 of its 32 displacement bits. Besides yielding a wrong displacement, the decoded instruction was 4 bytes long instead of 6, so the disassembler lost sync with the instruction stream from that point on.
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CALLS with a 32-bit displacement (FC FF) was decoded as an SP-relative memory access, "calls (d32,sp)". This form is PC-relative: the target is the address of the CALLS instruction plus the displacement, analogous to the 16-bit form (FA FF) which already decodes with d16_pc. With the fix, the operand is the resolved call target address.
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Thanks to @smx-smx and @sympho-ru for their contributions!