| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| qtrvsim-mingw32-v0.9.7.zip | 2024-02-15 | 19.1 MB | |
| qtrvsim-macos-v0.9.7.zip | 2024-02-15 | 42.4 MB | |
| qtrvsim-macos-v0.9.7.dmg | 2024-02-15 | 19.5 MB | |
| qtrvsim_0.9.7-1.debian.tar.xz | 2024-02-15 | 5.2 kB | |
| qtrvsim_0.9.7-1.dsc | 2024-02-15 | 928 Bytes | |
| qtrvsim.spec | 2024-02-15 | 2.6 kB | |
| qtrvsim_0.9.7.orig.tar.xz | 2024-02-15 | 1.5 MB | |
| PKGBUILD | 2024-02-15 | 687 Bytes | |
| appimage.yml | 2024-02-15 | 652 Bytes | |
| QtRvSim version 0.9.7 release source code.tar.gz | 2024-02-15 | 1.4 MB | |
| QtRvSim version 0.9.7 release source code.zip | 2024-02-15 | 1.6 MB | |
| README.md | 2024-02-15 | 1.4 kB | |
| Totals: 12 Items | 85.6 MB | 0 | |
- GUI: fix examples button crashes on Windows and sometimes other platforms
- GUI: fix crash when no tab is selected
- CI: add windows libs to artifacts and use more cores available
- CI: Make pack QT with Win artifact
- Project: Use the include directory for LibElf on macOS, Homebrew misses RISC-V
- Machine: set SXL and UXL to 64-bit XLEN for RV64
- Students work was funded by RPAPS 2023 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
- We thanks for actual funding to Czech Technical University https://www.cvut.cz/
For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim For Arch https://aur.archlinux.org/pkgbase/qtrvsim WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app
QtRvSim articles, presentations and their recordings as well as more about Computer Architectures courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/
The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course https://gitlab.fel.cvut.cz/b4m35pap/rvapo-vhdl and tested in GHDL simulation and on Zilinx Zynq and iCE-40 FPGA targets
