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Partially Reconfigurable Hardware


Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs

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This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary bottlenecks. The tools described in this project enable the hardware engineer to develop DPR-FPGA systems more effectively for rapid control system development.

For more information, related papers and user guide, please refer to:

Partially Reconfigurable Hardware Web Site


  • Highly concurrent framework for device control that decouples time sensitive hardware datapath from software;
  • Architecture for a concurrent control system that removes the impact of the FPGA’s internal partial reconfiguration on the processor with the OS and its system bus;
  • Software application programming interface (API) that allows Linux command line communication with DPR hardware modules;
  • Validated on Xilinx Virtex-5 DPR-FPGA (ML-505 development board).


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Additional Project Details



Intended Audience

Developers, Engineering, Architects

User Interface


Programming Language

C, VHDL/Verilog



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