PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool.
We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool.
VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design.
The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.
- Simple syntax for describing large circuits
- Hierarchical syntax for designing complicated circuits
- Ancillary files such as Bill of Materials, Reference Designator Mappings Table, and Layout Supplemental Information
- Concise and direct compiler messages