A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

Project Activity

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Categories

Electronic Design Automation (EDA)

License

GNU Library or Lesser General Public License version 2.0 (LGPLv2)

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Additional Project Details

Intended Audience

Information Technology

Programming Language

VHDL/Verilog, Java

Database Environment

XML-based

Related Categories

VHDL/Verilog Electronic Design Automation (EDA) Software, Java Electronic Design Automation (EDA) Software

Registered

2009-02-14
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