| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| logisim-evolution-5.0.0-x86_64.dmg | 2026-09-14 | 84.2 MB | |
| logisim-evolution-5.0.0-all.jar | 2026-09-12 | 54.4 MB | |
| logisim-evolution_5.0.0_amd64.deb | 2026-09-12 | 71.7 MB | |
| logisim-evolution-5.0.0-1.x86_64.rpm | 2026-09-12 | 71.7 MB | |
| logisim-evolution-5.0.0-windows-amd64.zip | 2026-09-12 | 77.4 MB | |
| logisim-evolution-5.0.0-windows-aarch64.zip | 2026-09-12 | 75.4 MB | |
| logisim-evolution-5.0.0-amd64.msi | 2026-09-12 | 79.1 MB | |
| logisim-evolution-5.0.0-aarch64.msi | 2026-09-12 | 77.2 MB | |
| logisim-evolution-5.0.0-aarch64.dmg | 2026-09-12 | 82.1 MB | |
| README.md | 2026-09-12 | 9.1 kB | |
| Version 5.0.0 source code.tar.gz | 2026-09-12 | 47.8 MB | |
| Version 5.0.0 source code.zip | 2026-09-12 | 50.6 MB | |
| Totals: 12 Items | 771.7 MB | 589 | |
- v5.0.0 (2026-09-12)
- Improved visual representation of Pull Resistor component (@V-Zemlyakov).
- Re-enabled SonarCloud analysis in the GitHub Actions build workflow (@zdimension).
- Added anti-aliasing preference to control anti-aliasing of UI elements (@V-Zemlyakov).
- Simplified Keyboard component buffer handling by removing redundant array-copy guards [#564] (@hewzhew).
- Set default gate shape to rectangular (IEC) for Russian locale (@V-Zemlyakov).
- Added a new signed/unsigned option to the multiplier component.(@Diogo-Valadares)
- Added "Show Bus Width" wire attribute to label multi-bit buses with a tick mark at Start, Center, or End (@V-Zemlyakov).
- Added Image component to insert custom bitmap images into circuits and subcircuit appearances.
- Added contributor guidance and an online component overview for the TTL library.
- Fixed packaged runtimes failing to launch when Java accessibility support is configured [#2398] (@hewzhew).
- Added "Find Action" omni-search, letting menu actions be found and run by typing part of their name, with fuzzy and acronym matching (e.g. "expim" or "ei" find "Export Image"). It opens from the Help menu, from Ctrl+Shift+A (configurable under Preferences > Hotkey settings), or by tapping Shift twice (switchable under Preferences > Window). It is built as a hub over pluggable search providers, so further sources of results can be added without changing the dialog. Its Add provider can select components for placement from the project's open libraries.
- Fixed FlatLaf "restricted native access" warning on newer Java versions.
- Fixed HDL generator tests failing when the "Use upper case for VHDL keywords" preference is disabled (@MarcinOrlowski)
- Improved file merging and export capabilities:
- Added ability to selectively merge individual circuits and subcircuit dependencies from a Logisim file.
- Added ability to export individual circuits along with dependent subcircuits into standalone Logisim files.
- Added conflict resolution dialog to replace, rename, or skip conflicting circuits.
- Added support for opening project files by dragging them into the application window.
- Added a Window menu option to hide or show the navigation pane.
- Added configurable shortcuts for selecting the default toolbar tools.
- Added ability to load multiple RAM or ROM memories from the command line
- Added an opt-in RAM data-bus mode where inactive output-enable drives separate outputs to high-impedance.
- Added Real-Time Clock component.
- Added Floating Point Constant component.
- Added FPGA HDL support for the Bit Finder component [#2890] (@hewzhew).
- Added 444 RGB (12 bit) color mode to the RGB Video component.
- Modified paste behavior to paste at current mouse location if it is on canvas.
- Added multiline Text Tool labels using Shift+Enter or multiline clipboard text.
- Fixed a regression that caused TestVector to fail when the circuit had subcircuits.
- Fixed TTL 7447 BI/RBO port to be an input/output port to allow cascading of blanking mode.
- Added TTL 7476: dual J-K Flip-flop with preset and clear.
- Added TTL 7493: 4-bit binary ripple counter.
- Added TTL 7438: quad dual-input NAND gate, open collector.
- Added TTL 74173: 4-bit D-type registers with 3-state outputs.
- Improved drawing appearance:
- Corrected font choice for default fonts in TikZ image exports.
- Corrected disjoint corners on Square Root arithmetic components.
- Corrected disjoint corners on unpressed Button components.
- Reduced line reordering errors in TikZ/SVG image exports.
- Improved dark theme (FlatLaf Dark / Darcula) color synchronization:
- Canvas background, grid dots, component outlines, icons, and signal wire colors now adapt to the active theme.
- Look and feel switching applies globally to all open windows without requiring a restart.
- Fixed gate negation bubbles, K-map text, expression overlines, and splitter bit-range labels to be visible on dark backgrounds.
- Replaced hard-coded hex color literals with named
DEFAULT_*/DARK_*constants in classAppPreferences.
- Added separate light and dark code editor theme preferences for HDL and assembly editors.
- Improved Timing Diagram recording and exports:
- Corrected vector and GIF exports.
- Corrected reset offsets, non-50% duty-cycle clocks, real-time traces, and RAM memory traces.
- Improved custom circuit appearance editing and dynamic appearance elements:
- Circuit attributes are shown when no item is selected.
- Dynamic elements preserve nested paths and can display nested Probe/Register values correctly.
- Corrected drag selection, selected-object attributes, and automatic switching to custom appearance.
- Improved memory and hex editor tools:
- Added a go-to-address control to the hex editor.
- Limited generated save previews for large memories.
- Clarified RAM and Dual Port RAM simulation reset behavior labels.
- Corrected memory display layout in exported graphics.
- Wide Counter components use compact grouped state rows in evolution appearance.
- RAM line-enable inputs now only write when enabled. Existing projects relying on unconnected line-enable inputs may need to connect those inputs explicitly.
- Random Generator now uses xoshiro256++ to produce full-width 64-bit pseudorandom values in simulation and generated HDL.
- Added HDL-language-aware label and circuit-name validation: VHDL remains case-insensitive, Verilog permits case-distinct names, and selecting no HDL permits non-HDL identifiers.
- Fixed several HDL and FPGA generation issues, including wide Random generator HDL, PortIO bubble ranges, scanning I/O constraints, and Xilinx download placeholder handling.
- Fixed FPGA component mappings losing their board highlights when the mapping dialog is reopened [#2933] (@hewzhew).
- Fixed output-only Port I/O components being reported as multiple drivers during FPGA netlist generation, and corrected the symmetric input-only endpoint direction [#2537] (@henriquejsza).
- Improved project editing stability:
- Layout zoom and scroll position are remembered separately for each circuit during a session.
- Circuits without a remembered view initially fit the window at up to 100% zoom and are centered.
- Moving components preserves component state.
- RAM components continue to notify their circuit of memory changes after being moved [#2873] (@henriquejsza).
- Floating subcircuit inputs now propagate floating values.
- Nested library tools resolve correctly.
- Text label editing handles menu-shortcut actions and in-place undo/redo consistently.
- No-op text edits no longer create undo actions.
- Improved VHDL editing and simulation UI:
- VHDL entity appearance is configured through entity properties.
- VHDL code view no longer paints a circuit canvas without a circuit.
- VHDL simulator log split pane remains recoverable after being maximized.
- Added a VHDL standard preference for QuestaSim/ModelSim validation and simulation.
- VHDL co-simulation now analyzes project-local entities in library order and preserves their canonical names for dependency resolution [#1350] (@hewzhew).
- Improved command-line output and localization:
- Command-line help now honors the selected locale.
- Invalid command-line option values now return a nonzero exit status.
- Intel/Altera FPGA downloads can select an exact Quartus cable with
--fpga-cable. - TTY table output includes bit widths in headers.
- Updated the command-line option reference to match the current interface [#1546] (@hewzhew).
- Localized the Assembly Viewer.
- Added and updated documentation for Telnet, FPGA Commander reports, the board editor, JAR libraries, wire values, transistor behavior, and unused-library save options.
- Added a default text-tool color preference and synchronized string-option preference updates.
- Component tree can now be filtered. Any part of the name matches, and multiple words match in any order.
- Added a Github Action check ensuring PRs also provide updated changelog (@MarcinOrlowski).
- Fixed
Line.matches()comparing transposed coordinates, causing identical lines to be treated as different and some different lines as identical [#2939] (@henriquejsza). - Added a Github Action check ensuring pull requests reference the open ticket they address (@MarcinOrlowski).
- Added a Github Action locking merged pull requests and the tickets they closed (@MarcinOrlowski).
- Fixed the DEB package refusing to install on Debian 12 and Ubuntu 22.04, by listing the
pre-
t64library names as alternative dependencies [#2959] (@MarcinOrlowski). - Many other bug fixes.
