| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| logisim-evolution-3.8.0-all.jar | 2022-10-02 | 26.3 MB | |
| logisim-evolution-3.8.0.dmg | 2022-10-02 | 78.7 MB | |
| logisim-evolution-3.8.0-1.x86_64.rpm | 2022-10-02 | 73.9 MB | |
| logisim-evolution-3.8.0-arm64.msi | 2022-10-02 | 72.7 MB | |
| logisim-evolution-3.8.0-x86.msi | 2022-10-02 | 74.0 MB | |
| logisim-evolution_3.8.0-1_amd64.deb | 2022-10-02 | 58.7 MB | |
| README.md | 2022-10-02 | 1.4 kB | |
| Version 3.8.0 source code.tar.gz | 2022-10-02 | 42.0 MB | |
| Version 3.8.0 source code.zip | 2022-10-02 | 44.3 MB | |
| Totals: 9 Items | 470.7 MB | 6 | |
Mainly a bug-fix release:
- Added reset value attribute to input pins
- Fixed boolean algebra minimal form bug
- Fixed random fill Rom bug
- Added TTL 74164, 74192 and 74193.
- Fixed off grid components bug that could lead to OutOfMemory error.
- Removed autolabler for tunnels, such that all get the same label in case of renaming.
- Fixed bug preventing TTL 7442, 7443 and 7444 from being placed on the circuit canvas.
- Sub-circuit can now be deleted with
DELETEkey, along withBACKSPACEused so far. - Fixed
Simulate->Timing Diagramnot opening when using "Nimbus" look and feel. - Fixed pressing
CTRL+0selecting the wrong element in the toolbar. - Fixed TTL 7485
7485HdlGeneratorgenerating wrong HDL type. - Fixed TTL 74139, 7447 outputting inverted logic
- Fixed TTL 74175, CLR inverted
- Fixed TTL 7436 pin arrangement
- Added TTL 74138: 3-line to 8-line decoder
- Added TTL 74240, 74241, 74244: octal buffers with three-state outputs.
- Added TTL 74245: octal bus transceivers with three-state outputs.
- Moved TTL 74266 to 747266, correctly reimplemented 74266 with open-collector outputs.
- Fixed TTL 74165, correct order of inputs, load asynchronously
- Added TTL 74166: 8-bit parallel-to-serial shift register with clear
- Removed fixed LM_License setting