Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

Project Samples

SMV editor, parser error - "pci.smv", cannot find module. SMV editor - "counter.smv" example. SMV editor, parser error - cannot find module. SMV editor, parser error - wrong boolean expression. BDD manipulation through Java code. BDD printout through Java debugger.

Project Activity

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Categories

Algorithms, Electronic Design Automation (EDA)

License

GNU Library or Lesser General Public License version 2.0 (LGPLv2)

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Additional Project Details

Operating Systems

BSD, Linux, Windows

Intended Audience

Advanced End Users, Developers, Education, Science/Research

User Interface

Eclipse

Programming Language

C, Java

Related Categories

C Algorithms, C Electronic Design Automation (EDA) Software, Java Algorithms, Java Electronic Design Automation (EDA) Software

Registered

2008-03-19
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